/*
**********************************************************************
*name: IE_stm32_ivt.S
*author: Samuel Igwe
*date: 08/04/2013
*description: Igbo Embedded stm32_ivt.S source
* the interrupt vector table starts with the initial
* stack address followed by the addresses of the function
* and ISR's. just allocate the space - leave it vacant
**********************************************************************
*/
.global stm32_ivt
.global stm32_ivt_end
.extern main
.equ STM32_SRAM_BASE, 0x20000000
.equ STM32_NUM_INT , 60
.data
.align 4
stm32_ivt: .word STM32_SRAM_BASE + (20 * 1024)
.word (main + 1)
.skip (14 * 4)
.skip (STM32_NUM_INT * 4)
stm32_ivt_end:
.text
Monday, August 5, 2013
IE_stm32_ivt.S
IE_stm32.c
/*
**********************************************************************
*name: IE_stm32.c
*author: Samuel Igwe
*date: 08/04/2013
*description: Igbo Embedded stm32.c source
**********************************************************************
*/
#include "IE_stm32.h"
#include "IE_tclib.h"
/*
**********************************************************************
*external reference to stm32_ivt
**********************************************************************
*/
#define STM32_RAM_BASE_ADDRESS 0x20000000
extern int stm32_ivt;
extern int stm32_ivt_end;
/*
**********************************************************************
*uart buffer and control
**********************************************************************
*/
#define STM32_UART_BUF_SIZE 64
struct STR_STM32_UART
{
char sbUartBuf[STM32_UART_BUF_SIZE + 1];
int wdMutex;
int wdBufCnt;
int wdDmaFlag;
}strUart;
/*
**********************************************************************
*8Mhz * 9 = 72Mhz. 100 clock rate (10mS) desired
**********************************************************************
*/
#define STM32_TIMER_TICK_RATE_PER_SEC 100
struct STR_STM32_SYSTICK
{
/*timer module*/
volatile unsigned int dwMsTick;
volatile unsigned int dwSeconds;
volatile unsigned int dwMsTotal;
/*a means to hook into the timer routine*/
void (*ptrFunc)(void);
}strSystick;
/*
**********************************************************************
*functions private to this module
**********************************************************************
*/
void stm32_init(void);
void stm32_rcc_cr_init(void);
void stm32_gpio_init(void);
void stm32_uart_init(void);
void stm32_nvic_init(void);
void stm32_timer_init(void);
void stm32_nvic_fault_isr(void);
void stm32_nvic_unknown_isr(void);
void stm32_nvic_systick_isr(void);
void stm32_uart_dequeue_buffer(void);
/*
**********************************************************************
*description: core init
*inputs: none
*note: ascii cart generator: digital form
* http://www.network-science.de/ascii/
**********************************************************************
*/
void stm32_init(void)
{
char *ptrBanner[] = {\
"+-++-++-++-+ +-++-++-++-++-++-++-++-+ +-++-++-++-++-++-++-++-++-+",\
"|I||g||b||o| |E||m||b||e||d||d||e||d| |C||o||r||t||e||x||-||m||3|",\
"+-++-++-++-+ +-++-++-++-++-++-++-++-+ +-++-++-++-++-++-++-++-++-+"};
unsigned char ptrNewline[] = {13,10,0};
int wdCount, wdTemp;
/*
**********************************************************************
*initialization should start with:
*reset control clock registers
*general purpose input output registers
*universal asynchronous receiver transmitter registers
*nested vectored interrupt controller registers
**********************************************************************
*/
stm32_rcc_cr_init();
stm32_gpio_init();
stm32_uart_init();
stm32_timer_init();
stm32_nvic_init();
/*
**********************************************************************
*write banner
**********************************************************************
*/
for(wdCount=0; wdCount < 3; wdCount++)
{
wdTemp = tclib_strlen(ptrNewline);
stm32_uart_puts(ptrNewline, wdTemp);
wdTemp = tclib_strlen((unsigned char *)ptrBanner[wdCount]);
stm32_uart_puts((unsigned char *)ptrBanner[wdCount], wdTemp);
}
wdTemp = tclib_strlen(ptrNewline);
stm32_uart_puts(ptrNewline, wdTemp);
}
/*
**********************************************************************
*description: delay wdUs ticks
*input: unsigned int wdUs = number of uS ticks to delay for
*note: use timer2. its tied to a 36Mhz reference (PCLK1)
**********************************************************************
*/
void stm32_timer_uS_delay(unsigned int wdUs)
{
volatile unsigned int wdTemp, wdPr;
if(wdUs > 1000000)
wdUs = 1000000;
/*adjust preload counter if greater than 1000*/
if(wdUs > 1000)
{
wdUs /= 1000;
wdPr = 36000;
}
else
wdPr = 36;
/*
**********************************************************************
*clear status
*clear interrupt enable reg
*clear control reg 2
*then
*setup prescaler value
*setup autoreload (for count up)
*clear the status register' UIF bit
*then set control reg 1 OPM + CEN
*finally
*loop on status register checking UIF
**********************************************************************
*/
(*PTR_STM32_TIM2_CR1) = 0;
(*PTR_STM32_TIM2_SR) = 0;
(*PTR_STM32_TIM2_DIER)= 0;
(*PTR_STM32_TIM2_CR2) = 0;
(*PTR_STM32_TIM2_PSC) = wdPr;
(*PTR_STM32_TIM2_ARR) = wdUs;
(*PTR_STM32_TIM2_SR) = STM32_TIM_SR_UIF;
wdTemp = STM32_TIM_CR1_OPM;
wdTemp |= STM32_TIM_CR1_CEN;
(*PTR_STM32_TIM2_CR1) = wdTemp;
do
{
wdTemp = (*PTR_STM32_TIM2_SR);
wdTemp &= STM32_TIM_SR_UIF;
}while(wdTemp != STM32_TIM_SR_UIF);
}
/*
**********************************************************************
*description: unhook timer services
*input: void (*ptrFunc)(void) = pointer to function to call
**********************************************************************
*/
void stm32_systick_unhook_services(void(*ptrFunc)(void))
{
if(strSystick.ptrFunc == ptrFunc)
strSystick.ptrFunc = NULL;
}
/*
**********************************************************************
*description: hook timer services
*input: void (*ptrFunc)(void) = pointer to function to call
**********************************************************************
*/
void stm32_systick_hook_services(void (*ptrFunc)(void))
{
if(strSystick.ptrFunc == NULL)
strSystick.ptrFunc = ptrFunc;
}
/*
**********************************************************************
*description: get seconds
*output: int wdSeconds
**********************************************************************
*/
int stm32_systick_get_seconds(void)
{
return strSystick.dwSeconds;
}
/*
**********************************************************************
*description: get millisecond tick
*output: int wdMsTick value
**********************************************************************
*/
int stm32_systick_get_mS_tick(void)
{
return strSystick.dwMsTick;
}
/*
**********************************************************************
*description: nvic un-install isr routine
*inputs: unsigned int wdIrqNum = irq number (0 - 255)
*note: handlers are just regular C functions. this routine
* un-installes handlers for vectors above 16!
**********************************************************************
*/
void stm32_nvic_uninstall_isr(unsigned int wdIrqNum)
{
volatile unsigned int wdByteIdx, wdBitIdx, *ptrTemp;
if(wdIrqNum > 255)
return;
/*install generic handler into table*/
ptrTemp = (volatile unsigned int *)&stm32_ivt;
ptrTemp += 16; /*get passed system tables*/
*(ptrTemp + wdIrqNum) = ((unsigned int)(stm32_nvic_unknown_isr) | 0x1);
/*enable the particular bit*/
wdByteIdx = (wdIrqNum / 32);
wdBitIdx = (wdIrqNum % 32);
ptrTemp = PTR_STM32_NVIC_INTCE_BASE;
ptrTemp += wdByteIdx;
(*ptrTemp)= (1 << wdBitIdx);
}
/*
**********************************************************************
*description: nvic install isr routine
*inputs: unsigned int wdIrqNum = irq number (0 - 255)
* unsigned int wdIsrAddr= address of handler
*note: handlers are just regular C functions. this routine
* installs handlers for vectors above 16!
**********************************************************************
*/
void stm32_nvic_install_isr(unsigned int wdIrqNum,\
unsigned int wdIsrAddr)
{
volatile unsigned int wdByteIdx, wdBitIdx, *ptrTemp, wdTemp;
if(wdIrqNum > 255)
return;
/*install handler into table*/
ptrTemp = (volatile unsigned int *)&stm32_ivt;
ptrTemp += 16; /*get passed system tables*/
*(ptrTemp + wdIrqNum) = (unsigned int)(wdIsrAddr |0x1);
/*set the priority low (high number) so as not to conflict with systick*/
wdByteIdx = (wdIrqNum / 4);
wdBitIdx = (wdIrqNum % 4);
wdTemp = (wdIrqNum >> 4); /*build prio from irqnum*/
if(wdTemp == 0)
wdTemp++;
ptrTemp = PTR_STM32_NVIC_INTP_BASE;
ptrTemp += wdByteIdx;
(*ptrTemp)= ((wdTemp << 4) << (wdBitIdx << 8)); /*bits [7:4] of prio*/
/*enable the particular bit*/
wdByteIdx = (wdIrqNum / 32);
wdBitIdx = (wdIrqNum % 32);
ptrTemp = PTR_STM32_NVIC_INTSE_BASE;
ptrTemp += wdByteIdx;
(*ptrTemp)= (1 << wdBitIdx);
}
/*
**********************************************************************
*description: nvic fault isr handler
*note: handlers are just regular C functions
**********************************************************************
*/
void stm32_nvic_fault_isr(void)
{
volatile unsigned int wdTemp;
/*determine which interrupt led me here*/
wdTemp = (*PTR_STM32_NVIC_INTCS);
wdTemp &= STM32_NVIC_INTCS_VECTACTIVE_MASK;
wdTemp >>= STM32_NVIC_INTCS_VECTACTIVE_OFFSET;
/*call stm32_uart_dequeue_buffer() twice to run dma and release semaphore*/
stm32_uart_dequeue_buffer();
stm32_uart_dequeue_buffer();
tclib_printf("nvic: vector= %d\n", wdTemp);
wdTemp = (*PTR_STM32_NVIC_SHCSR);
tclib_printf("nvic: shcsr = %x\t", wdTemp);
wdTemp = (*PTR_STM32_NVIC_BFAR);
tclib_printf("nvic: bfar = %x\t", wdTemp);
/*call stm32_uart_dequeue_buffer() twice to run dma and release semaphore*/
stm32_uart_dequeue_buffer();
stm32_uart_dequeue_buffer();
while(1)
;
}
/*
**********************************************************************
*description: nvic unknown isr handler
*note: handlers are just regular C functions
**********************************************************************
*/
void stm32_nvic_unknown_isr(void)
{
volatile unsigned int wdIrqNum;
/*determine which interrupt led me here*/
wdIrqNum = (*PTR_STM32_NVIC_INTCS);
wdIrqNum &= STM32_NVIC_INTCS_VECTACTIVE_MASK;
wdIrqNum >>= STM32_NVIC_INTCS_VECTACTIVE_OFFSET;
if(wdIrqNum < 16)
tclib_printf("nvic_irq_vector %d\n", wdIrqNum);
else
tclib_printf("nvic_irq %d\n", (wdIrqNum - 16));
}
/*
**********************************************************************
*description: nvic systick isr handler
*note: handlers are just regular C functions
* flash LED1 after a second
**********************************************************************
*/
void stm32_nvic_systick_isr(void)
{
volatile unsigned int wdTemp, wdPin;
strSystick.dwMsTotal++;
strSystick.dwMsTick++;
if(strSystick.dwMsTick == STM32_TIMER_TICK_RATE_PER_SEC)
{
strSystick.dwMsTick = 0;
strSystick.dwSeconds++;
/*flash LED1 once a second*/
wdPin = STM32_GPIO_PIN_LED1;
wdTemp = (*PTR_STM32_GPIO_B_ODR);
wdTemp &= (1 << wdPin);
wdTemp ^= (1 << wdPin);
(*PTR_STM32_GPIO_B_ODR) = wdTemp;
}
/*call user function is requested*/
if(strSystick.ptrFunc != NULL)
strSystick.ptrFunc();
/*dequeue uart buffer*/
stm32_uart_dequeue_buffer();
}
/*
**********************************************************************
*description: uart dequeue routine
*notes: should be called from the systick handler. this is how
* it is supposed to work
* check if dma is in progress (wdDmaFlag)
* if so check if dma completed
* if so
* clear wdDmaFlag
* clear ISR flag
* release semaphore
* else
* return
* else
* check if wdBufCnt > 0
* if so atttempt to acquire semaphore once
* if failure exit
* else
* start dma
* set wdDmaFlag to active
* clear wdBufCnt
*
*DO NOT EXECUTE A "while" or "do-while" IN THIS ROUTINE
**********************************************************************
*/
void stm32_uart_dequeue_buffer(void)
{
volatile unsigned int wdTemp;
if(strUart.wdDmaFlag == TRUE)
{
wdTemp = (*PTR_STM32_DMA1_ISR);
wdTemp &= STM32_DMA_ISR_TCIF_MASK;
if(wdTemp == 0)
return;
(*PTR_STM32_DMA1_ISR) = STM32_DMA_IFCR_CTCIF_MASK;
(*PTR_STM32_DMA1_CCR4) = 0;
strUart.wdDmaFlag = FALSE;
tclib_release_semaphore((unsigned int *)&strUart.wdMutex);
return;
}
else
{
if(strUart.wdBufCnt == 0)
return;
wdTemp = tclib_acquire_semaphore((unsigned int *)&strUart.wdMutex);
if(wdTemp == 0)
return;
(*PTR_STM32_DMA1_CNDTR4)= strUart.wdBufCnt;
(*PTR_STM32_DMA1_CPAR4) = (unsigned int)(PTR_STM32_UART1_DR);
(*PTR_STM32_DMA1_CMAR4) = (unsigned int)&strUart.sbUartBuf;
(*PTR_STM32_DMA1_ISR) = STM32_DMA_IFCR_CTCIF_MASK;
wdTemp = STM32_DMA_CCR_MSIZE_8;
wdTemp |= STM32_DMA_CCR_PSIZE_8;
wdTemp |= STM32_DMA_CCR_MINC;
wdTemp |= STM32_DMA_CCR_DIR_FROM_MEMORY;
wdTemp |= STM32_DMA_CCR_EN;
(*PTR_STM32_DMA1_CCR4) = wdTemp;
strUart.wdDmaFlag = TRUE;
strUart.wdBufCnt = 0;
}
}
/*
**********************************************************************
*description: uart queue routine
*inputs: char *ptrBuffer = pointer to memory
* int wdBytelen = byte length
*notes: this is the generic uart i/o routine. heres how it is
* supposed to work:
* stm32_uart_puts() will be used to transmit both chars
* and strings of characters
*
* while(bytelen != 0)
* acquire semaphore
* copy characters into buffer
**********************************************************************
*/
void stm32_uart_puts(unsigned char *ptrBuffer, int wdBytelen)
{
volatile unsigned int wdTemp, wdXferCnt;
unsigned char *ptrTemp;
while(wdBytelen != 0)
{
/*wait until space frees up*/
do
{
wdTemp = (STM32_UART_BUF_SIZE - strUart.wdBufCnt);
}while(wdTemp == 0);
/*get semaphore*/
do
{
wdTemp = tclib_acquire_semaphore((unsigned int *)&strUart.wdMutex);
}while(wdTemp == 0);
/*determine maximum number of characters i can queue up*/
if(wdBytelen > STM32_UART_BUF_SIZE)
wdXferCnt = STM32_UART_BUF_SIZE;
else
wdXferCnt = wdBytelen;
/*determine how much space is left in the uart buffer*/
wdTemp = STM32_UART_BUF_SIZE - strUart.wdBufCnt;
if(wdXferCnt > wdTemp)
wdXferCnt = wdTemp;
/*memcpy the data over*/
ptrTemp = (unsigned char *)(strUart.sbUartBuf + strUart.wdBufCnt);
tclib_memcpy((unsigned char *)ptrTemp, ptrBuffer, wdXferCnt);
/*adjust strUart index and wdBytelen*/
strUart.wdBufCnt += wdXferCnt;
wdBytelen -= wdXferCnt;
ptrBuffer += wdXferCnt;
/*release semaphore*/
tclib_release_semaphore((unsigned int *)&strUart.wdMutex);
}
}
/*
**********************************************************************
*description: free running timer to be used to time/guage progress
*input: void
*note: use timer3. its tied to a 36Mhz reference (PCLK1)
**********************************************************************
*/
void stm32_timer_init(void)
{
volatile unsigned int wdTemp;
/*
**********************************************************************
*clear control reg 2
*then
*setup prescaler value
*setup autoreload (for count up)
*then set control reg 1 OPM + CEN
**********************************************************************
*/
(*PTR_STM32_TIM3_CR1) = 0;
(*PTR_STM32_TIM3_DIER)= 0;
(*PTR_STM32_TIM3_CR2) = 0;
(*PTR_STM32_TIM3_PSC) = 36;
(*PTR_STM32_TIM3_ARR) = 0xffffffff;
wdTemp = STM32_TIM_CR1_DIR_UP;
wdTemp |= STM32_TIM_CR1_CEN;
(*PTR_STM32_TIM3_CR1) = wdTemp;
}
/*
**********************************************************************
*description: nvic initialization function
*note: setup the systick clock and handler and the interrupts
* for usb (low and high priority)
**********************************************************************
*/
void stm32_nvic_init(void)
{
volatile unsigned int wdTemp, *ptrTemp, wdCount;
tclib_memset((unsigned char *)&strSystick, 0, sizeof(strSystick));
/*
**********************************************************************
*install handlers for all vector positions
*skip positions 0 = thread stack and 1 = reset address
*dont hardcode size of table - determine it with stm32_ivt and _end
**********************************************************************
*/
ptrTemp = (volatile unsigned int *)&stm32_ivt;
wdTemp = (&stm32_ivt_end - &stm32_ivt);
for(wdCount=2; wdCount<wdTemp; wdCount++)
{
if(wdCount <= 6)
ptrTemp[wdCount] = ((unsigned int)(stm32_nvic_fault_isr)\
| 0x1);
else
{
if(wdCount == 15)
ptrTemp[wdCount] = ((unsigned int)(stm32_nvic_systick_isr)\
| 0x1);
else
ptrTemp[wdCount] = ((unsigned int)(stm32_nvic_unknown_isr)\
| 0x1);
}
}
/*
**********************************************************************
*setup exception and interrupt priorities. CRUCIAL because of a bug in
*my code I discovered (because of leaving priorities set to the
*default) that caused a branch into the usb isr to PREVENT premption
*by the systick handler which was holding a mutex. deadlock ...
*
*zero out sytem handler priority registers. give them all max priority
*
*set all external interrupt priorities to 0x8
**********************************************************************
*/
(*PTR_STM32_NVIC_SHPR_1) = 0;
(*PTR_STM32_NVIC_SHPR_2) = 0;
(*PTR_STM32_NVIC_SHPR_3) = 0;
ptrTemp = PTR_STM32_NVIC_INTP_BASE;
wdTemp = (&stm32_ivt_end - &stm32_ivt);
wdTemp -= 16; /*subtract exceptions table*/
if((wdTemp & 0x3) != 0) /*really (wdTemp % 4)*/
wdTemp += 4; /*for non integer multiples*/
wdTemp >>= 2; /*there are 4 prio in one reg*/
for(wdCount=0; wdCount<= wdTemp; wdCount++)
ptrTemp[wdCount] = 0x88888888; /*only bits [7:4] are used but*/
/*
**********************************************************************
*the internal rc clock and external crystal clock are both 8Mhz. Setup
*the pll to generate the maximum clock rate for the cortex-m3 - that
*is 72Mhz. the systick reload register will be configured to generate
*an interrupt 100 times a second
**********************************************************************
*/
(*PTR_STM32_NVIC_SYSTRV) = 720000;
/*
**********************************************************************
*set 8 byte stack alignment and context restoration
*set the interrupt vector table
*set and enable the systick interrupt
**********************************************************************
*/
wdTemp = STM32_NVIC_CCR_STKALIGN_QWORD;
wdTemp |= STM32_NVIC_CCR_DIV_0_TRP;
(*PTR_STM32_NVIC_CCR) = wdTemp;
wdTemp = (unsigned int )&stm32_ivt;
wdTemp -= STM32_RAM_BASE_ADDRESS;
wdTemp |= STM32_NVIC_VTOR_TBLBASE_RAM;
(*PTR_STM32_NVIC_VTOR) = wdTemp;
wdTemp = STM32_NVIC_STCSR_CLKSOURCE_CORE;
wdTemp |= STM32_NVIC_STCSR_TICKINT;
wdTemp |= STM32_NVIC_STCSR_ENABLE;
(*PTR_STM32_NVIC_SYSTCSR) = wdTemp;
/*
**********************************************************************
*now enable interrupts
*enable interrupt set enable for the first 16 vectors
**********************************************************************
*/
asm("dsb");
wdTemp = 1 << 2; /*nmi*/
wdTemp |= 1 << 3; /*hard*/
wdTemp |= 1 << 4; /*mmu*/
wdTemp |= 1 << 5; /*bus*/
wdTemp |= 1 << 6; /*usage*/
wdTemp |= 1 << 15; /*systick*/
(*PTR_STM32_NVIC_INTSE_BASE) = wdTemp;
asm("cpsie i");
}
/*
**********************************************************************
*description: setup uart for 115200
* setup
* baud rate register
* control reg1
* control reg2
* control reg3
**********************************************************************
*/
void stm32_uart_init(void)
{
volatile unsigned int wdTemp;
(*PTR_STM32_UART1_BRR) = 0x271;
wdTemp = STM32_UART_CR1_UE;
wdTemp |= STM32_UART_CR1_RE;
wdTemp |= STM32_UART_CR1_TE;
(*PTR_STM32_UART1_CR1) = wdTemp;
(*PTR_STM32_UART1_CR2) = 0;
wdTemp = STM32_UART_CR3_EIE;
wdTemp |= STM32_UART_CR3_DMAT;
(*PTR_STM32_UART1_CR3) = wdTemp;
/*initialize strUart*/
tclib_memset((unsigned char *)&strUart, 0, sizeof(strUart));
}
/*
**********************************************************************
*description: setup general purpose I/O pins
* uart
* led
* switches
**********************************************************************
*/
void stm32_gpio_init(void)
{
volatile unsigned int wdTemp, wdMask;
wdTemp = STM32_GPIO_PIN_UART_TX - 8;
wdMask = ((STM32_GPIO_CNF_OUT_ALT_OPEN_DRAIN << 2) | STM32_GPIO_MODE_OUTPUT_2MHZ)\
<< (wdTemp << 2);
wdTemp = STM32_GPIO_PIN_UART_RX - 8;
wdMask |= ((STM32_GPIO_CNF_IN_FLOATING << 2) | STM32_GPIO_MODE_INPUT_MODE)\
<< (wdTemp << 2);
(*PTR_STM32_GPIO_A_CRH) = wdMask;
wdTemp = STM32_GPIO_PIN_LED1 - 8;
wdMask = ((STM32_GPIO_CNF_OUT_GEN_PUSH_PULL << 2) | STM32_GPIO_MODE_OUTPUT_2MHZ)\
<< (wdTemp << 2);
wdTemp = STM32_GPIO_PIN_LED2 - 8;
wdMask |= ((STM32_GPIO_CNF_OUT_GEN_PUSH_PULL << 2) | STM32_GPIO_MODE_OUTPUT_2MHZ)\
<< (wdTemp << 2);
(*PTR_STM32_GPIO_B_CRH) = wdMask;
wdTemp = STM32_GPIO_PIN_SW1;
wdMask = ((STM32_GPIO_CNF_IN_PULL_UP_DOWN << 2) | STM32_GPIO_MODE_INPUT_MODE)\
<< (wdTemp << 2);
wdTemp = STM32_GPIO_PIN_SW2;
wdMask |= ((STM32_GPIO_CNF_IN_PULL_UP_DOWN << 2) | STM32_GPIO_MODE_INPUT_MODE)\
<< (wdTemp << 2);
(*PTR_STM32_GPIO_C_CRL) = wdMask;
(*PTR_STM32_GPIO_B_BRR) = (1 << STM32_GPIO_PIN_LED1 | 1 << STM32_GPIO_PIN_LED2);
}
/*
**********************************************************************
*description: setup reset clock register and enable peripherals
*note: reset then enable peripherals I need. note that this
* routine should be called before any core peripherals
* are enabled
**********************************************************************
*/
void stm32_rcc_cr_init(void)
{
volatile unsigned int wdTemp;
/*
**********************************************************************
*enable the various clocks and set pll and divider values
**********************************************************************
*/
wdTemp = STM32_RCC_CFGR_SW_PLL << STM32_RCC_CFGR_SW_OFFSET;
wdTemp |= STM32_RCC_CFGR_HPRE_NODIV << STM32_RCC_CFGR_HPRE_OFFSET;
wdTemp |= STM32_RCC_CFGR_PPRE1_2 << STM32_RCC_CFGR_PPRE1_OFFSET;
wdTemp |= STM32_RCC_CFGR_PPRE2_NODIV << STM32_RCC_CFGR_PPRE2_OFFSET;
wdTemp |= STM32_RCC_CFGR_PLLSRC;
wdTemp |= (9 - STM32_RCC_CFGR_PLLMUL_ADJUSTMENT) << STM32_RCC_CFGR_PLLMUL_OFFSET;
wdTemp |= STM32_RCC_CFGR_MCO_HSE;
(*PTR_STM32_RCC_CFGR) = wdTemp;
wdTemp = STM32_RCC_CR_HSEON;
wdTemp |= STM32_RCC_CR_CSSON;
wdTemp |= STM32_RCC_CR_PLLON;
(*PTR_STM32_RCC_CR) = wdTemp;
/*
**********************************************************************
*wait for the pll and high speed external clock to be ready ...
**********************************************************************
*/
do
{
wdTemp = (*PTR_STM32_RCC_CR);
wdTemp &= (STM32_RCC_CR_PLLRDY | STM32_RCC_CR_HSERDY);
}while(wdTemp != (STM32_RCC_CR_PLLRDY | STM32_RCC_CR_HSERDY));
/*
**********************************************************************
*reset the peripherals
*then zero out the peripherals
**********************************************************************
*/
wdTemp = STM32_RCC_APB2RSTR_UART1RST;
wdTemp |= STM32_RCC_APB2RSTR_IOPDRST;
wdTemp |= STM32_RCC_APB2RSTR_IOPCRST;
wdTemp |= STM32_RCC_APB2RSTR_IOPBRST;
wdTemp |= STM32_RCC_APB2RSTR_IOPARST;
wdTemp |= STM32_RCC_APB2RSTR_AFIORST;
(*PTR_STM32_RCC_APB2RSTR) = wdTemp;
wdTemp = STM32_RCC_APB1RSTR_PWRRST;
wdTemp |= STM32_RCC_APB1RSTR_USBRST;
wdTemp |= STM32_RCC_APB1RSTR_TIM5RST;
wdTemp |= STM32_RCC_APB1RSTR_TIM4RST;
wdTemp |= STM32_RCC_APB1RSTR_TIM3RST;
wdTemp |= STM32_RCC_APB1RSTR_TIM2RST;
(*PTR_STM32_RCC_APB1RSTR) = wdTemp;
(*PTR_STM32_RCC_APB2RSTR) = 0;
(*PTR_STM32_RCC_APB1RSTR) = 0;
/*
**********************************************************************
*enable the peripherals
**********************************************************************
*/
wdTemp = STM32_RCC_AHBENR_CRCEN;
wdTemp |= STM32_RCC_AHBENR_SRAMEN;
wdTemp |= STM32_RCC_AHBENR_DMA2EN;
wdTemp |= STM32_RCC_AHBENR_DMA1EN;
(*PTR_STM32_RCC_AHBENR) = wdTemp;
wdTemp = STM32_RCC_APB2ENR_UART1EN;
wdTemp |= STM32_RCC_APB2ENR_IOPDEN;
wdTemp |= STM32_RCC_APB2ENR_IOPCEN;
wdTemp |= STM32_RCC_APB2ENR_IOPBEN;
wdTemp |= STM32_RCC_APB2ENR_IOPAEN;
wdTemp |= STM32_RCC_APB2ENR_AFIOEN;
(*PTR_STM32_RCC_APB2ENR) = wdTemp;
wdTemp = STM32_RCC_APB1ENR_PWREN;
wdTemp |= STM32_RCC_APB1ENR_USBEN;
wdTemp |= STM32_RCC_APB1ENR_TIM5EN;
wdTemp |= STM32_RCC_APB1ENR_TIM4EN;
wdTemp |= STM32_RCC_APB1ENR_TIM3EN;
wdTemp |= STM32_RCC_APB1ENR_TIM2EN;
(*PTR_STM32_RCC_APB1ENR) = wdTemp;
wdTemp = STM32_RCC_BDCR_RTCEN;
wdTemp |= STM32_RCC_BDCR_RTCSEL_LSE << STM32_RCC_BDCR_RTCSEL_OFFSET;
wdTemp |= STM32_RCC_BDCR_LSEON;
(*PTR_STM32_RCC_BDCR) = wdTemp;
}
Monday, July 29, 2013
IE_stm32_dma.h
/*
**********************************************************************
*name: IE_stm32_dma.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_dma header
**********************************************************************
*/
#ifndef IE_STM32_DMA
#define IE_STM32_DMA
#define PTR_STM32_DMA1_BASE 0x40020000
#define PTR_STM32_DMA2_BASE 0x40020400
/*
**********************************************************************
*dma interrupt status register
**********************************************************************
*/
#define PTR_STM32_DMA1_ISR (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 0)
#define PTR_STM32_DMA2_ISR (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 0)
#define STM32_DMA_ISR_TEIF_MASK 0x8888888
#define STM32_DMA_ISR_HTIF_MASK 0x4444444
#define STM32_DMA_ISR_TCIF_MASK 0x2222222
#define STM32_DMA_ISR_GIF_MASK 0x1111111
/*
**********************************************************************
*dma interrupt flag clear register
**********************************************************************
*/
#define PTR_STM32_DMA1_IFCR (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 4)
#define PTR_STM32_DMA2_IFCR (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 4)
#define STM32_DMA_IFCR_CTEIF_MASK 0x8888888
#define STM32_DMA_IFCR_CHTIF_MASK 0x4444444
#define STM32_DMA_IFCR_CTCIF_MASK 0x2222222
#define STM32_DMA_IFCR_CGIF_MASK 0x1111111
/*
**********************************************************************
*dma channel x configuration register
**********************************************************************
*/
#define PTR_STM32_DMA1_CCR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 8)
#define PTR_STM32_DMA1_CCR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 28)
#define PTR_STM32_DMA1_CCR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 48)
#define PTR_STM32_DMA1_CCR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 68)
#define PTR_STM32_DMA1_CCR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 88)
#define PTR_STM32_DMA1_CCR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 108)
#define PTR_STM32_DMA1_CCR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 128)
#define PTR_STM32_DMA2_CCR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 8)
#define PTR_STM32_DMA2_CCR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 28)
#define PTR_STM32_DMA2_CCR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 48)
#define PTR_STM32_DMA2_CCR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 68)
#define PTR_STM32_DMA2_CCR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 88)
#define STM32_DMA_CCR_MEM2MEM_ENABLED (1 << 14)
#define STM32_DMA_CCR_PL_OFFSET 12
#define STM32_DMA_CCR_PL_MASK 0x3
#define STM32_DMA_CCR_PL_LOW (0 << 12)
#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
#define STM32_DMA_CCR_PL_HIGH (2 << 12)
#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
#define STM32_DMA_CCR_MSIZE_OFFSET 10
#define STM32_DMA_CCR_MSIZE_MASK 0x3
#define STM32_DMA_CCR_MSIZE_8 (0 << 10)
#define STM32_DMA_CCR_MSIZE_16 (1 << 10)
#define STM32_DMA_CCR_MSIZE_32 (2 << 10)
#define STM32_DMA_CCR_PSIZE_OFFSET 8
#define STM32_DMA_CCR_PSIZE_MASK 0x3
#define STM32_DMA_CCR_PSIZE_8 (0 << 8)
#define STM32_DMA_CCR_PSIZE_16 (1 << 8)
#define STM32_DMA_CCR_PSIZE_32 (2 << 8)
#define STM32_DMA_CCR_MINC (1 << 7)
#define STM32_DMA_CCR_PINC (1 << 6)
#define STM32_DMA_CCR_CIRC (1 << 5)
#define STM32_DMA_CCR_DIR_FROM_PERIPHERAL (0 << 4)
#define STM32_DMA_CCR_DIR_FROM_MEMORY (1 << 4)
#define STM32_DMA_CCR_TEIE (1 << 3)
#define STM32_DMA_CCR_HTIE (1 << 2)
#define STM32_DMA_CCR_TCIE (1 << 1)
#define STM32_DMA_CCR_EN (1 << 0)
/*
**********************************************************************
*dma channel x number of data register
**********************************************************************
*/
#define PTR_STM32_DMA1_CNDTR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 12)
#define PTR_STM32_DMA1_CNDTR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 32)
#define PTR_STM32_DMA1_CNDTR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 52)
#define PTR_STM32_DMA1_CNDTR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 72)
#define PTR_STM32_DMA1_CNDTR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 92)
#define PTR_STM32_DMA1_CNDTR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 112)
#define PTR_STM32_DMA1_CNDTR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 132)
#define PTR_STM32_DMA2_CNDTR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 12)
#define PTR_STM32_DMA2_CNDTR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 32)
#define PTR_STM32_DMA2_CNDTR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 52)
#define PTR_STM32_DMA2_CNDTR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 72)
#define PTR_STM32_DMA2_CNDTR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 92)
#define STM32_DMA_CNDTR_MASK 0x0ffff
/*
**********************************************************************
*dma channel x peripheral address register
**********************************************************************
*/
#define PTR_STM32_DMA1_CPAR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 16)
#define PTR_STM32_DMA1_CPAR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 36)
#define PTR_STM32_DMA1_CPAR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 56)
#define PTR_STM32_DMA1_CPAR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 76)
#define PTR_STM32_DMA1_CPAR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 96)
#define PTR_STM32_DMA1_CPAR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 116)
#define PTR_STM32_DMA1_CPAR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 136)
#define PTR_STM32_DMA2_CPAR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 16)
#define PTR_STM32_DMA2_CPAR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 36)
#define PTR_STM32_DMA2_CPAR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 56)
#define PTR_STM32_DMA2_CPAR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 76)
#define PTR_STM32_DMA2_CPAR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 96)
/*
**********************************************************************
*dma channel x memory address register
**********************************************************************
*/
#define PTR_STM32_DMA1_CMAR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 20)
#define PTR_STM32_DMA1_CMAR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 40)
#define PTR_STM32_DMA1_CMAR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 60)
#define PTR_STM32_DMA1_CMAR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 80)
#define PTR_STM32_DMA1_CMAR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 100)
#define PTR_STM32_DMA1_CMAR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 120)
#define PTR_STM32_DMA1_CMAR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 140)
#define PTR_STM32_DMA2_CMAR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 20)
#define PTR_STM32_DMA2_CMAR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 40)
#define PTR_STM32_DMA2_CMAR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 60)
#define PTR_STM32_DMA2_CMAR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 80)
#define PTR_STM32_DMA2_CMAR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 100)
#endif
Thursday, July 18, 2013
IE_stm32_usb.h
/*
**********************************************************************
*name: IE_stm32_usb.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_usb header
**********************************************************************
*/
#ifndef IE_STM32_USB
#define IE_STM32_USB
#define PTR_STM32_USB_BASE 0x40005c00
#define PTR_STM32_USB_EPRAM 0x40006000
/*
**********************************************************************
*usb base address
**********************************************************************
*/
#define PTR_STM32_USB_BTABLE (volatile unsigned int *)(PTR_STM32_USB_BASE + 80)
/*
**********************************************************************
*usb control register
**********************************************************************
*/
#define PTR_STM32_USB_CNTR (volatile unsigned int *)(PTR_STM32_USB_BASE + 64)
#define STM32_USB_CNTR_CTRM (1 << 15)
#define STM32_USB_CNTR_PMAOVRM (1 << 14)
#define STM32_USB_CNTR_ERRM (1 << 13)
#define STM32_USB_CNTR_WKUPM (1 << 12)
#define STM32_USB_CNTR_SUSPM (1 << 11)
#define STM32_USB_CNTR_RESETM (1 << 10)
#define STM32_USB_CNTR_SOFM (1 << 9)
#define STM32_USB_CNTR_ESOFM (1 << 8)
#define STM32_USB_CNTR_RESUME (1 << 4)
#define STM32_USB_CNTR_FSUSP (1 << 3)
#define STM32_USB_CNTR_LP_MODE (1 << 2)
#define STM32_USB_CNTR_PDWN (1 << 1)
#define STM32_USB_CNTR_FRES (1 << 0)
/*
**********************************************************************
*usb interrupt status register
**********************************************************************
*/
#define PTR_STM32_USB_ISTR (volatile unsigned int *)(PTR_STM32_USB_BASE + 68)
#define STM32_USB_ISTR_CTR (1 << 15)
#define STM32_USB_ISTR_PMAOVR (1 << 14)
#define STM32_USB_ISTR_ERR (1 << 13)
#define STM32_USB_ISTR_WKUP (1 << 12)
#define STM32_USB_ISTR_SUSP (1 << 11)
#define STM32_USB_ISTR_RESET (1 << 10)
#define STM32_USB_ISTR_SOF (1 << 9)
#define STM32_USB_ISTR_ESOF (1 << 8)
#define STM32_USB_ISTR_DIR_MASK (1 << 4)
#define STM32_USB_ISTR_DIR_IN (0 << 4)
#define STM32_USB_ISTR_DIR_OUT (1 << 4)
#define STM32_USB_ISTR_EP_ID_OFFSET 0
#define STM32_USB_ISTR_EP_ID_MASK (0x0f << 0)
/*
**********************************************************************
*usb interrupt status register
**********************************************************************
*/
#define PTR_STM32_USB_FNR (volatile unsigned int *)(PTR_STM32_USB_BASE + 72)
#define STM32_USB_FNR_RXDP (1 << 15)
#define STM32_USB_FNR_RXDM (1 << 14)
#define STM32_USB_FNR_LCK (1 << 13)
#define STM32_USB_FNR_LSOF_OFFSET 11
#define STM32_USB_FNR_LSOF_MASK (0x3 << 11)
#define STM32_USB_FNR_FN_OFFSET 0
#define STM32_USB_FNR_FN_MASK (0x7ff << 0)
/*
**********************************************************************
*usb device address register
**********************************************************************
*/
#define PTR_STM32_USB_DADDR (volatile unsigned int *)(PTR_STM32_USB_BASE + 76)
#define STM32_USB_DADDR_EF (1 << 7)
#define STM32_USB_DADDR_ADD_OFFSET 0
#define STM32_USB_DADDR_ADD_MASK (0x7f << 0)
/*
**********************************************************************
*usb endpoint specific register
**********************************************************************
*/
#define PTR_STM32_USB_EP0R (volatile unsigned int *)(PTR_STM32_USB_BASE + 0)
#define PTR_STM32_USB_EP1R (volatile unsigned int *)(PTR_STM32_USB_BASE + 4)
#define PTR_STM32_USB_EP2R (volatile unsigned int *)(PTR_STM32_USB_BASE + 8)
#define PTR_STM32_USB_EP3R (volatile unsigned int *)(PTR_STM32_USB_BASE + 12)
#define PTR_STM32_USB_EP4R (volatile unsigned int *)(PTR_STM32_USB_BASE + 16)
#define PTR_STM32_USB_EP5R (volatile unsigned int *)(PTR_STM32_USB_BASE + 20)
#define PTR_STM32_USB_EP6R (volatile unsigned int *)(PTR_STM32_USB_BASE + 24)
#define PTR_STM32_USB_EP7R (volatile unsigned int *)(PTR_STM32_USB_BASE + 28)
#define STM32_USB_EPR_CTR_RX (1 << 15)
#define STM32_USB_EPR_DTOG_RX (1 << 14)
#define STM32_USB_EPR_DTOG_RX_OFFSET 14
#define STM32_USB_EPR_STAT_RX_OFFSET 12
#define STM32_USB_EPR_STAT_RX_MASK (0x3 << 12)
#define STM32_USB_EPR_STAT_RX_DISABLE 0
#define STM32_USB_EPR_STAT_RX_STALL 1
#define STM32_USB_EPR_STAT_RX_NAK 2
#define STM32_USB_EPR_STAT_RX_VALID 3
#define STM32_USB_EPR_SETUP (1 << 11)
#define STM32_USB_EPR_EP_TYPE_OFFSET 9
#define STM32_USB_EPR_EP_TYPE_MASK (0x3 << 9)
#define STM32_USB_EPR_EP_TYPE_BULK 0
#define STM32_USB_EPR_EP_TYPE_CONTROL 1
#define STM32_USB_EPR_EP_TYPE_ISO 2
#define STM32_USB_EPR_EP_TYPE_INTERRUPT 3
#define STM32_USB_EPR_EP_KIND (1 << 8)
#define STM32_USB_EPR_CTR_TX (1 << 7)
#define STM32_USB_EPR_DTOG_TX (1 << 6)
#define STM32_USB_EPR_DTOG_TX_OFFSET 6
#define STM32_USB_EPR_STAT_TX_OFFSET 4
#define STM32_USB_EPR_STAT_TX_MASK (0x3 << 4)
#define STM32_USB_EPR_STAT_TX_DISABLE 0
#define STM32_USB_EPR_STAT_TX_STALL 1
#define STM32_USB_EPR_STAT_TX_NAK 2
#define STM32_USB_EPR_STAT_TX_VALID 3
#define STM32_USB_EPR_EA_OFFSET 0
#define STM32_USB_EPR_EA_MASK (0x0f << 0)
/*
**********************************************************************
*usb buffer description table. I can put the buffer description table
*anyway in the 512 memory I choose to put it in the beginning. this
*should be addressed as short (16 bits)
*
*transmission buffer address n
**********************************************************************
*/
#define PTR_STM32_USB_ADDR0_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 0)
#define PTR_STM32_USB_ADDR1_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 8)
#define PTR_STM32_USB_ADDR2_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 16)
#define PTR_STM32_USB_ADDR3_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 24)
#define PTR_STM32_USB_ADDR4_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 32)
#define PTR_STM32_USB_ADDR5_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 40)
#define PTR_STM32_USB_ADDR6_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 48)
#define PTR_STM32_USB_ADDR7_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 56)
#define STM32_USB_ADDR_TX_OFFSET 1
#define STM32_USB_ADDR_TX_MASK (0x7fff << 1)
/*
**********************************************************************
*transmission byte count n
**********************************************************************
*/
#define PTR_STM32_USB_COUNT0_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 2)
#define PTR_STM32_USB_COUNT1_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 10)
#define PTR_STM32_USB_COUNT2_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 18)
#define PTR_STM32_USB_COUNT3_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 26)
#define PTR_STM32_USB_COUNT4_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 34)
#define PTR_STM32_USB_COUNT5_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 42)
#define PTR_STM32_USB_COUNT6_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 50)
#define PTR_STM32_USB_COUNT7_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 58)
#define STM32_USB_COUNT_TX_OFFSET 0
#define STM32_USB_COUNT_TX_MASK (0x3ff << 0)
/*
**********************************************************************
*reception buffer address n
**********************************************************************
*/
#define PTR_STM32_USB_ADDR0_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 4)
#define PTR_STM32_USB_ADDR1_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 12)
#define PTR_STM32_USB_ADDR2_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 20)
#define PTR_STM32_USB_ADDR3_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 28)
#define PTR_STM32_USB_ADDR4_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 36)
#define PTR_STM32_USB_ADDR5_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 44)
#define PTR_STM32_USB_ADDR6_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 52)
#define PTR_STM32_USB_ADDR7_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 60)
#define STM32_USB_ADDR_RX_OFFSET 1
#define STM32_USB_ADDR_RX_MASK (0x7fff << 1)
/*
**********************************************************************
*reception byte count n
**********************************************************************
*/
#define PTR_STM32_USB_COUNT0_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 6)
#define PTR_STM32_USB_COUNT1_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 14)
#define PTR_STM32_USB_COUNT2_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 22)
#define PTR_STM32_USB_COUNT3_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 30)
#define PTR_STM32_USB_COUNT4_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 38)
#define PTR_STM32_USB_COUNT5_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 46)
#define PTR_STM32_USB_COUNT6_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 54)
#define PTR_STM32_USB_COUNT7_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 62)
#define STM32_USB_COUNT_RX_BL_SIZE_MASK (1 << 15)
#define STM32_USB_COUNT_RX_BL_SIZE_2BYTE (0 << 15)
#define STM32_USB_COUNT_RX_BL_SIZE_32BYTE (1 << 15)
#define STM32_USB_COUNT_RX_NUM_BLOCK_OFFSET 10
#define STM32_USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << 10)
#define STM32_USB_COUNT_RX_OFFSET 0
#define STM32_USB_COUNT_RX_MASK (0x3ff << 0)
/*
**********************************************************************
*module routines
**********************************************************************
*/
void stm32_usb_init(void);
void stm32_usb_pre_reset_setup(unsigned int wdEndPNum,\
unsigned int wdEndPType,\
unsigned int wdEndPSize);
void stm32_usb_post_reset_setup(unsigned int wdEndPNum,\
unsigned int wdEndPType,\
unsigned int wdEndPSize);
int stm32_usb_endp_send_packet(unsigned int wdEndPNum,\
unsigned char *ptrBuffer,\
unsigned int wdEndPSize,\
unsigned int wdBytelen);
int stm32_usb_build_endp_descriptors(unsigned int wdEndPNum,\
unsigned int wdEndPType,\
unsigned int wdEndPSize,\
unsigned int *ptrDescAddr,\
unsigned int wdLclPktAddr);
int stm32_usb_endp_get_packet(unsigned int wdEndPNum,\
unsigned char *ptrBuffer,\
unsigned int wdBytelen);
void stm32_usb_connect_pullup(unsigned int wdPin);
void stm32_usb_disconnect_pullup(unsigned int wdPin);
#endif
IE_stm32_uart.h
/*
**********************************************************************
*name: IE_stm32_uart.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_uart header
**********************************************************************
*/
#ifndef IE_STM32_UART
#define IE_STM32_UART
#define PTR_STM32_UART1_BASE 0x40013800
#define PTR_STM32_UART2_BASE 0x40004400
#define PTR_STM32_UART3_BASE 0x40004800
#define PTR_STM32_UART4_BASE 0x40004c00
/*
**********************************************************************
*uart status register
**********************************************************************
*/
#define PTR_STM32_UART1_SR (volatile unsigned int *)(PTR_STM32_UART1_BASE + 0)
#define PTR_STM32_UART2_SR (volatile unsigned int *)(PTR_STM32_UART2_BASE + 0)
#define PTR_STM32_UART3_SR (volatile unsigned int *)(PTR_STM32_UART3_BASE + 0)
#define PTR_STM32_UART4_SR (volatile unsigned int *)(PTR_STM32_UART4_BASE + 0)
#define STM32_UART_SR_CTS (1 << 9)
#define STM32_UART_SR_LBD (1 << 8)
#define STM32_UART_SR_TXE (1 << 7)
#define STM32_UART_SR_TC (1 << 6)
#define STM32_UART_SR_RXNE (1 << 5)
#define STM32_UART_SR_IDLE (1 << 4)
#define STM32_UART_SR_ORE (1 << 3)
#define STM32_UART_SR_NE (1 << 2)
#define STM32_UART_SR_FE (1 << 1)
#define STM32_UART_SR_PE (1 << 0)
/*
**********************************************************************
*uart data register
**********************************************************************
*/
#define PTR_STM32_UART1_DR (volatile unsigned int *)(PTR_STM32_UART1_BASE + 4)
#define PTR_STM32_UART2_DR (volatile unsigned int *)(PTR_STM32_UART2_BASE + 4)
#define PTR_STM32_UART3_DR (volatile unsigned int *)(PTR_STM32_UART3_BASE + 4)
#define PTR_STM32_UART4_DR (volatile unsigned int *)(PTR_STM32_UART4_BASE + 4)
#define STM32_UART_DR_MASK (0x1ff << 0)
/*
**********************************************************************
*uart baud rate register
*using a 72Mhz clock and a baudrate of 115200 means this register
*should be set to 0x291
**********************************************************************
*/
#define PTR_STM32_UART1_BRR (volatile unsigned int *)(PTR_STM32_UART1_BASE + 8)
#define PTR_STM32_UART2_BRR (volatile unsigned int *)(PTR_STM32_UART2_BASE + 8)
#define PTR_STM32_UART3_BRR (volatile unsigned int *)(PTR_STM32_UART3_BASE + 8)
#define PTR_STM32_UART4_BRR (volatile unsigned int *)(PTR_STM32_UART4_BASE + 8)
#define STM32_UART_BRR_DIV_MANTISSA_OFFSET 4
#define STM32_UART_BRR_DIV_MANTISSA_MASK (0x0fff << 4)
#define STM32_UART_BRR_DIV_FRACTION_OFFSET 0
#define STM32_UART_BRR_DIV_FRACTION_MASK (0x0f << 0)
/*
**********************************************************************
*uart control register1
**********************************************************************
*/
#define PTR_STM32_UART1_CR1 (volatile unsigned int *)(PTR_STM32_UART1_BASE + 12)
#define PTR_STM32_UART2_CR1 (volatile unsigned int *)(PTR_STM32_UART2_BASE + 12)
#define PTR_STM32_UART3_CR1 (volatile unsigned int *)(PTR_STM32_UART3_BASE + 12)
#define PTR_STM32_UART4_CR1 (volatile unsigned int *)(PTR_STM32_UART4_BASE + 12)
#define STM32_UART_CR1_UE (1 << 13)
#define STM32_UART_CR1_M (1 << 12)
#define STM32_UART_CR1_WAKE (1 << 11)
#define STM32_UART_CR1_PCE (1 << 10)
#define STM32_UART_CR1_PS (1 << 9)
#define STM32_UART_CR1_PEIE (1 << 8)
#define STM32_UART_CR1_TXEIE (1 << 7)
#define STM32_UART_CR1_TCIE (1 << 6)
#define STM32_UART_CR1_RXNEIE (1 << 5)
#define STM32_UART_CR1_IDLEIE (1 << 4)
#define STM32_UART_CR1_TE (1 << 3)
#define STM32_UART_CR1_RE (1 << 2)
#define STM32_UART_CR1_RWU (1 << 1)
#define STM32_UART_CR1_SBK (1 << 0)
/*
**********************************************************************
*uart control register2
**********************************************************************
*/
#define PTR_STM32_UART1_CR2 (volatile unsigned int *)(PTR_STM32_UART1_BASE + 16)
#define PTR_STM32_UART2_CR2 (volatile unsigned int *)(PTR_STM32_UART2_BASE + 16)
#define PTR_STM32_UART3_CR2 (volatile unsigned int *)(PTR_STM32_UART3_BASE + 16)
#define PTR_STM32_UART4_CR2 (volatile unsigned int *)(PTR_STM32_UART4_BASE + 16)
#define STM32_UART_CR2_LINEN (1 << 14)
#define STM32_UART_CR2_STOP_OFFSET 12
#define STM32_UART_CR2_STOP_MASK (0x3 << 12)
#define STM32_UART_CR2_STOP_1_BIT 0
#define STM32_UART_CR2_STOP_0P5_BIT 1
#define STM32_UART_CR2_STOP_2_BIT 2
#define STM32_UART_CR2_STOP_1P5_BIT 3
#define STM32_UART_CR2_CLKEN (1 << 11)
#define STM32_UART_CR2_CPOL (1 << 10)
#define STM32_UART_CR2_CPHA (1 << 9)
#define STM32_UART_CR2_LBCL (1 << 8)
#define STM32_UART_CR2_LBDIE (1 << 6)
#define STM32_UART_CR2_LBDL (1 << 5)
#define STM32_UART_CR2_ADD_OFFSET 0
#define STM32_UART_CR2_ADD_MASK (0x0f << 0)
/*
**********************************************************************
*uart control register3
**********************************************************************
*/
#define PTR_STM32_UART1_CR3 (volatile unsigned int *)(PTR_STM32_UART1_BASE + 20)
#define PTR_STM32_UART2_CR3 (volatile unsigned int *)(PTR_STM32_UART2_BASE + 20)
#define PTR_STM32_UART3_CR3 (volatile unsigned int *)(PTR_STM32_UART3_BASE + 20)
#define PTR_STM32_UART4_CR3 (volatile unsigned int *)(PTR_STM32_UART4_BASE + 20)
#define STM32_UART_CR3_CTSIE (1 << 10)
#define STM32_UART_CR3_CTSE (1 << 9)
#define STM32_UART_CR3_RTSE (1 << 8)
#define STM32_UART_CR3_DMAT (1 << 7)
#define STM32_UART_CR3_DMAR (1 << 6)
#define STM32_UART_CR3_SCEN (1 << 5)
#define STM32_UART_CR3_NACK (1 << 4)
#define STM32_UART_CR3_HDSEL (1 << 3)
#define STM32_UART_CR3_IRLP (1 << 2)
#define STM32_UART_CR3_IREN (1 << 1)
#define STM32_UART_CR3_EIE (1 << 0)
/*
**********************************************************************
*uart control register3
**********************************************************************
*/
#define PTR_STM32_UART1_GTPR (volatile unsigned int *)(PTR_STM32_UART1_BASE + 24)
#define PTR_STM32_UART2_GTPR (volatile unsigned int *)(PTR_STM32_UART2_BASE + 24)
#define PTR_STM32_UART3_GTPR (volatile unsigned int *)(PTR_STM32_UART3_BASE + 24)
#define PTR_STM32_UART4_GTPR (volatile unsigned int *)(PTR_STM32_UART4_BASE + 24)
#define STM32_UART_CR3_GT_OFFSET 8
#define STM32_UART_CR3_GT_MASK (0x0ff << 8)
#define STM32_UART_CR3_PSC_OFFSET 0
#define STM32_UART_CR3_PSC_MASK (0x0ff << 0)
#endif
IE_stm32_rstcc.h
/*
**********************************************************************
*name: IE_stm32_rstcc.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_rstcc header
**********************************************************************
*/
#ifndef IE_STM32_RSTCC
#define IE_STM32_RSTCC
#define PTR_STM32_RCC_BASE 0x40021000
/*
**********************************************************************
*clock control register
**********************************************************************
*/
#define PTR_STM32_RCC_CR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 0)
#define STM32_RCC_CR_PLLRDY (1 << 25)
#define STM32_RCC_CR_PLLON (1 << 24)
#define STM32_RCC_CR_CSSON (1 << 19)
#define STM32_RCC_CR_HSEBYP (1 << 18)
#define STM32_RCC_CR_HSERDY (1 << 17)
#define STM32_RCC_CR_HSEON (1 << 16)
#define STM32_RCC_CR_HSICAL_OFFSET 8
#define STM32_RCC_CR_HSICAL_MASK (0x0ff << 8)
#define STM32_RCC_CR_HSITRIM_OFFSET 3
#define STM32_RCC_CR_HSITRIM_MASK (0x1f << 3)
#define STM32_RCC_CR_HSIRDY (1 << 1)
#define STM32_RCC_CR_HSION (1 << 0)
/*
**********************************************************************
*clock configuration register
**********************************************************************
*/
#define PTR_STM32_RCC_CFGR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 4)
#define STM32_RCC_CFGR_MCO_OFFSET 24
#define STM32_RCC_CFGR_MCO_MASK (0x7 << 24)
#define STM32_RCC_CFGR_MCO_NOCLK (0 << 24)
#define STM32_RCC_CFGR_MCO_SYSCLK (4 << 24)
#define STM32_RCC_CFGR_MCO_HSI (5 << 24)
#define STM32_RCC_CFGR_MCO_HSE (6 << 24)
#define STM32_RCC_CFGR_MCO_PLL (7 << 24)
#define STM32_RCC_CFGR_USBPRE (1 << 22)
#define STM32_RCC_CFGR_PLLMUL_OFFSET 18
#define STM32_RCC_CFGR_PLLMUL_MASK (0x0f << 18)
#define STM32_RCC_CFGR_PLLMUL_ADJUSTMENT 2
#define STM32_RCC_CFGR_PLLXTPRE (1 << 17)
#define STM32_RCC_CFGR_PLLSRC (1 << 16)
#define STM32_RCC_CFGR_ADCPRE_OFFSET 14
#define STM32_RCC_CFGR_ADCPRE_MASK (0x3 << 14)
#define STM32_RCC_CFGR_ADCPRE_BY_2 0
#define STM32_RCC_CFGR_ADCPRE_BY_4 1
#define STM32_RCC_CFGR_ADCPRE_BY_6 2
#define STM32_RCC_CFGR_ADCPRE_BY_8 3
#define STM32_RCC_CFGR_PPRE2_OFFSET 11
#define STM32_RCC_CFGR_PPRE2_MASK (0x7 << 11)
#define STM32_RCC_CFGR_PPRE2_NODIV 0
#define STM32_RCC_CFGR_PPRE2_BY_2 4
#define STM32_RCC_CFGR_PPRE2_BY_4 5
#define STM32_RCC_CFGR_PPRE2_BY_8 6
#define STM32_RCC_CFGR_PPRE2_BY_16 7
#define STM32_RCC_CFGR_PPRE1_OFFSET 8
#define STM32_RCC_CFGR_PPRE1_MASK (0x7 << 8)
#define STM32_RCC_CFGR_PPRE1_NODIV 0
#define STM32_RCC_CFGR_PPRE1_2 4
#define STM32_RCC_CFGR_PPRE1_4 5
#define STM32_RCC_CFGR_PPRE1_8 6
#define STM32_RCC_CFGR_PPRE1_16 7
#define STM32_RCC_CFGR_HPRE_OFFSET 4
#define STM32_RCC_CFGR_HPRE_MASK (0x0f << 4)
#define STM32_RCC_CFGR_HPRE_NODIV 0
#define STM32_RCC_CFGR_HPRE_BY_2 9
#define STM32_RCC_CFGR_HPRE_BY_4 10
#define STM32_RCC_CFGR_HPRE_BY_16 11
#define STM32_RCC_CFGR_HPRE_BY_64 12
#define STM32_RCC_CFGR_HPRE_BY_128 13
#define STM32_RCC_CFGR_HPRE_BY_256 14
#define STM32_RCC_CFGR_HPRE_BY_512 15
#define STM32_RCC_CFGR_SWS_OFFSET 2
#define STM32_RCC_CFGR_SWS_MASK (0x3 << 2)
#define STM32_RCC_CFGR_SWS_HSI 0
#define STM32_RCC_CFGR_SWS_HSE 1
#define STM32_RCC_CFGR_SWS_PLL 2
#define STM32_RCC_CFGR_SW_OFFSET 0
#define STM32_RCC_CFGR_SW_MASK (0x3 << 0)
#define STM32_RCC_CFGR_SW_HSI 0
#define STM32_RCC_CFGR_SW_HSE 1
#define STM32_RCC_CFGR_SW_PLL 2
/*
**********************************************************************
*clock interrupt register
**********************************************************************
*/
#define PTR_STM32_RCC_CIR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 8)
#define STM32_RCC_CIR_CSSC (1 << 24)
#define STM32_RCC_CIR_PLLRDYC (1 << 20)
#define STM32_RCC_CIR_HSERDYC (1 << 19)
#define STM32_RCC_CIR_HSIRDYC (1 << 18)
#define STM32_RCC_CIR_LSERDYC (1 << 17)
#define STM32_RCC_CIR_LSIRDYC (1 << 16)
#define STM32_RCC_CIR_PLLRDYIE (1 << 12)
#define STM32_RCC_CIR_HSERDYIE (1 << 11)
#define STM32_RCC_CIR_HSIRDYIE (1 << 10)
#define STM32_RCC_CIR_LSERDYIE (1 << 9)
#define STM32_RCC_CIR_LSIRDYIE (1 << 8)
#define STM32_RCC_CIR_CSSF (1 << 7)
#define STM32_RCC_CIR_PLLRDYF (1 << 4)
#define STM32_RCC_CIR_HSERDYF (1 << 3)
#define STM32_RCC_CIR_HSIRDYF (1 << 2)
#define STM32_RCC_CIR_LSERDYF (1 << 1)
#define STM32_RCC_CIR_LSIRDYF (1 << 0)
/*
**********************************************************************
*apb2 peripheral reset register
**********************************************************************
*/
#define PTR_STM32_RCC_APB2RSTR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 12)
#define STM32_RCC_APB2RSTR_TIM11RST (1 << 21)
#define STM32_RCC_APB2RSTR_TIM10RST (1 << 20)
#define STM32_RCC_APB2RSTR_TIM9RST (1 << 19)
#define STM32_RCC_APB2RSTR_ADC3RST (1 << 15)
#define STM32_RCC_APB2RSTR_UART1RST (1 << 14)
#define STM32_RCC_APB2RSTR_TIM8RST (1 << 13)
#define STM32_RCC_APB2RSTR_SPI1RST (1 << 12)
#define STM32_RCC_APB2RSTR_TIM1RST (1 << 11)
#define STM32_RCC_APB2RSTR_ADC2RST (1 << 10)
#define STM32_RCC_APB2RSTR_ADC1RST (1 << 9)
#define STM32_RCC_APB2RSTR_IOPGRST (1 << 8)
#define STM32_RCC_APB2RSTR_IOPFRST (1 << 7)
#define STM32_RCC_APB2RSTR_IOPERST (1 << 6)
#define STM32_RCC_APB2RSTR_IOPDRST (1 << 5)
#define STM32_RCC_APB2RSTR_IOPCRST (1 << 4)
#define STM32_RCC_APB2RSTR_IOPBRST (1 << 3)
#define STM32_RCC_APB2RSTR_IOPARST (1 << 2)
#define STM32_RCC_APB2RSTR_AFIORST (1 << 0)
/*
**********************************************************************
*apb1 peripheral reset register
**********************************************************************
*/
#define PTR_STM32_RCC_APB1RSTR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 16)
#define STM32_RCC_APB1RSTR_DACRST (1 << 29)
#define STM32_RCC_APB1RSTR_PWRRST (1 << 28)
#define STM32_RCC_APB1RSTR_BKPRST (1 << 27)
#define STM32_RCC_APB1RSTR_CANRST (1 << 25)
#define STM32_RCC_APB1RSTR_USBRST (1 << 23)
#define STM32_RCC_APB1RSTR_I2C2RST (1 << 22)
#define STM32_RCC_APB1RSTR_I2C1RST (1 << 21)
#define STM32_RCC_APB1RSTR_UART5RST (1 << 20)
#define STM32_RCC_APB1RSTR_UART4RST (1 << 19)
#define STM32_RCC_APB1RSTR_UART3RST (1 << 18)
#define STM32_RCC_APB1RSTR_UART2RST (1 << 17)
#define STM32_RCC_APB1RSTR_SPI3RST (1 << 15)
#define STM32_RCC_APB1RSTR_SPI2RST (1 << 14)
#define STM32_RCC_APB1RSTR_WWDGRST (1 << 11)
#define STM32_RCC_APB1RSTR_TIM14RST (1 << 8)
#define STM32_RCC_APB1RSTR_TIM13RST (1 << 7)
#define STM32_RCC_APB1RSTR_TIM12RST (1 << 6)
#define STM32_RCC_APB1RSTR_TIM7RST (1 << 5)
#define STM32_RCC_APB1RSTR_TIM6RST (1 << 4)
#define STM32_RCC_APB1RSTR_TIM5RST (1 << 3)
#define STM32_RCC_APB1RSTR_TIM4RST (1 << 2)
#define STM32_RCC_APB1RSTR_TIM3RST (1 << 1)
#define STM32_RCC_APB1RSTR_TIM2RST (1 << 0)
/*
**********************************************************************
*ahb peripheral clock enable register
**********************************************************************
*/
#define PTR_STM32_RCC_AHBENR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 20)
#define STM32_RCC_AHBENR_SDIOEN (1 << 10)
#define STM32_RCC_AHBENR_FSMCEN (1 << 8)
#define STM32_RCC_AHBENR_CRCEN (1 << 6)
#define STM32_RCC_AHBENR_FLITFEN (1 << 4)
#define STM32_RCC_AHBENR_SRAMEN (1 << 2)
#define STM32_RCC_AHBENR_DMA2EN (1 << 1)
#define STM32_RCC_AHBENR_DMA1EN (1 << 0)
/*
**********************************************************************
*apb2 peripheral clock enable register
**********************************************************************
*/
#define PTR_STM32_RCC_APB2ENR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 24)
#define STM32_RCC_APB2ENR_TIM11EN (1 << 21)
#define STM32_RCC_APB2ENR_TIM10EN (1 << 20)
#define STM32_RCC_APB2ENR_TIM9EN (1 << 19)
#define STM32_RCC_APB2ENR_ADC3EN (1 << 15)
#define STM32_RCC_APB2ENR_UART1EN (1 << 14)
#define STM32_RCC_APB2ENR_TIM8EN (1 << 13)
#define STM32_RCC_APB2ENR_SPI1EN (1 << 12)
#define STM32_RCC_APB2ENR_TIM1EN (1 << 11)
#define STM32_RCC_APB2ENR_ADC2EN (1 << 10)
#define STM32_RCC_APB2ENR_ADC1EN (1 << 9)
#define STM32_RCC_APB2ENR_IOPGEN (1 << 8)
#define STM32_RCC_APB2ENR_IOPFEN (1 << 7)
#define STM32_RCC_APB2ENR_IOPEEN (1 << 6)
#define STM32_RCC_APB2ENR_IOPDEN (1 << 5)
#define STM32_RCC_APB2ENR_IOPCEN (1 << 4)
#define STM32_RCC_APB2ENR_IOPBEN (1 << 3)
#define STM32_RCC_APB2ENR_IOPAEN (1 << 2)
#define STM32_RCC_APB2ENR_AFIOEN (1 << 0)
/*
**********************************************************************
*apb1 peripheral clock enable register
**********************************************************************
*/
#define PTR_STM32_RCC_APB1ENR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 28)
#define STM32_RCC_APB1ENR_DACEN (1 << 29)
#define STM32_RCC_APB1ENR_PWREN (1 << 28)
#define STM32_RCC_APB1ENR_BKPEN (1 << 27)
#define STM32_RCC_APB1ENR_CANEN (1 << 25)
#define STM32_RCC_APB1ENR_USBEN (1 << 23)
#define STM32_RCC_APB1ENR_I2C2EN (1 << 22)
#define STM32_RCC_APB1ENR_I2C1EN (1 << 21)
#define STM32_RCC_APB1ENR_UART5EN (1 << 20)
#define STM32_RCC_APB1ENR_UART4EN (1 << 19)
#define STM32_RCC_APB1ENR_UART3EN (1 << 18)
#define STM32_RCC_APB1ENR_UART2EN (1 << 17)
#define STM32_RCC_APB1ENR_SPI3EN (1 << 15)
#define STM32_RCC_APB1ENR_SPI2EN (1 << 14)
#define STM32_RCC_APB1ENR_WWDGEN (1 << 11)
#define STM32_RCC_APB1ENR_TIM14EN (1 << 8)
#define STM32_RCC_APB1ENR_TIM13EN (1 << 7)
#define STM32_RCC_APB1ENR_TIM12EN (1 << 6)
#define STM32_RCC_APB1ENR_TIM7EN (1 << 5)
#define STM32_RCC_APB1ENR_TIM6EN (1 << 4)
#define STM32_RCC_APB1ENR_TIM5EN (1 << 3)
#define STM32_RCC_APB1ENR_TIM4EN (1 << 2)
#define STM32_RCC_APB1ENR_TIM3EN (1 << 1)
#define STM32_RCC_APB1ENR_TIM2EN (1 << 0)
/*
**********************************************************************
*backup domain control register
**********************************************************************
*/
#define PTR_STM32_RCC_BDCR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 32)
#define STM32_RCC_BDCR_BDRST (1 << 16)
#define STM32_RCC_BDCR_RTCEN (1 << 15)
#define STM32_RCC_BDCR_RTCSEL_OFFSET 8
#define STM32_RCC_BDCR_RTCSEL_MASK (0x3 << 8)
#define STM32_RCC_BDCR_RTCSEL_NOCLK 0
#define STM32_RCC_BDCR_RTCSEL_LSE 1
#define STM32_RCC_BDCR_RTCSEL_HSE 3
#define STM32_RCC_BDCR_LSEBYP (1 << 2)
#define STM32_RCC_BDCR_LSERDY (1 << 1)
#define STM32_RCC_BDCR_LSEON (1 << 0)
/*
**********************************************************************
*control/status register
**********************************************************************
*/
#define PTR_STM32_RCC_CSR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 36)
#define STM32_RCC_CSR_LPWRRSTF (1 << 31)
#define STM32_RCC_CSR_WWDGRSTF (1 << 30)
#define STM32_RCC_CSR_IWDGRSTF (1 << 29)
#define STM32_RCC_CSR_SETRSTF (1 << 28)
#define STM32_RCC_CSR_PORRSTF (1 << 27)
#define STM32_RCC_CSR_PINRSTF (1 << 26)
#define STM32_RCC_CSR_RMVF (1 << 24)
#define STM32_RCC_CSR_LSIRDY (1 << 1)
#define STM32_RCC_CSR_LSION (1 << 0)
#endif
IE_stm32_gpio.h
/*
**********************************************************************
*name: IE_stm32_gpio.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_gpio header
**********************************************************************
*/
#ifndef IE_STM32_GPIO
#define IE_STM32_GPIO
#define PTR_STM32_GPIO_A_BASE 0x40010800
#define PTR_STM32_GPIO_B_BASE 0x40010c00
#define PTR_STM32_GPIO_C_BASE 0x40011000
#define PTR_STM32_GPIO_D_BASE 0x40011400
/*
**********************************************************************
*port configuration #defines
**********************************************************************
*/
#define STM32_GPIO_CNF0_OFFSET 2
#define STM32_GPIO_CNF_MASK 3
#define STM32_GPIO_CNF_IN_ANALOG 0
#define STM32_GPIO_CNF_IN_FLOATING 1
#define STM32_GPIO_CNF_IN_PULL_UP_DOWN 2
#define STM32_GPIO_CNF_OUT_GEN_PUSH_PULL 0
#define STM32_GPIO_CNF_OUT_GEN_OPEN_DRAIN 1
#define STM32_GPIO_CNF_OUT_ALT_PUSH_PULL 2
#define STM32_GPIO_CNF_OUT_ALT_OPEN_DRAIN 3
#define STM32_GPIO_MODE1_OFFSET 4
#define STM32_GPIO_MODE_INPUT_MODE 0
#define STM32_GPIO_MODE_OUTPUT_10MHZ 1
#define STM32_GPIO_MODE_OUTPUT_2MHZ 2
#define STM32_GPIO_MODE_OUTPUT_50MHZ 3
/*
**********************************************************************
*port configuration register low
**********************************************************************
*/
#define PTR_STM32_GPIO_A_CRL (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 0)
#define PTR_STM32_GPIO_B_CRL (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 0)
#define PTR_STM32_GPIO_C_CRL (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 0)
#define PTR_STM32_GPIO_D_CRL (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 0)
/*
**********************************************************************
*port configuration register high
**********************************************************************
*/
#define PTR_STM32_GPIO_A_CRH (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 4)
#define PTR_STM32_GPIO_B_CRH (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 4)
#define PTR_STM32_GPIO_C_CRH (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 4)
#define PTR_STM32_GPIO_D_CRH (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 4)
/*
**********************************************************************
*port input data register
**********************************************************************
*/
#define PTR_STM32_GPIO_A_IDR (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 8)
#define PTR_STM32_GPIO_B_IDR (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 8)
#define PTR_STM32_GPIO_C_IDR (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 8)
#define PTR_STM32_GPIO_D_IDR (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 8)
#define STM32_GPIO_IDR_MASK 0x0ffff
/*
**********************************************************************
*port output data register
**********************************************************************
*/
#define PTR_STM32_GPIO_A_ODR (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 12)
#define PTR_STM32_GPIO_B_ODR (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 12)
#define PTR_STM32_GPIO_C_ODR (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 12)
#define PTR_STM32_GPIO_D_ODR (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 12)
#define STM32_GPIO_ODR_MASK 0x0ffff
/*
**********************************************************************
*port bit set/reset register
**********************************************************************
*/
#define PTR_STM32_GPIO_A_BSRR (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 16)
#define PTR_STM32_GPIO_B_BSRR (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 16)
#define PTR_STM32_GPIO_C_BSRR (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 16)
#define PTR_STM32_GPIO_D_BSRR (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 16)
#define STM32_GPIO_BSRR_BR_MASK (0x0ffff << 16)
#define STM32_GPIO_BSRR_BS_MASK (0x0ffff << 0)
/*
**********************************************************************
*port bit reset register
**********************************************************************
*/
#define PTR_STM32_GPIO_A_BRR (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 20)
#define PTR_STM32_GPIO_B_BRR (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 20)
#define PTR_STM32_GPIO_C_BRR (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 20)
#define PTR_STM32_GPIO_D_BRR (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 20)
#define STM32_GPIO_BR_MASK 0x0ffff
/*
**********************************************************************
*port configuration lock register
**********************************************************************
*/
#define PTR_STM32_GPIO_A_LCKR (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 24)
#define PTR_STM32_GPIO_B_LCKR (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 24)
#define PTR_STM32_GPIO_C_LCKR (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 24)
#define PTR_STM32_GPIO_D_LCKR (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 24)
#define STM32_GPIO_LCKR_MASK 0x1ffff
#define STM32_GPIO_LCKR_LCKK 0x10000
#endif
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