Phase 3: MPU

Per the ARM cortex r1p1 technical reference manual, the cortex-M3 includes (optional) MPU (which the ST32 cores do not have but the LPC cores do). This memory protection unit has 8 regions.

I plan on only using 4 of these regions.
region 0 will span the block of the default memory map designated "code" and "data". That would be 0x0000 0000 to 0x3fff ffff. The attributes will be:
strongly ordered
executable
cached

region 1 will span the block of the default memory map designated "peripherals". That would be 0x4000 0000 to 0x5fff ffff.  The attributes will be:
strongly ordered
non executable
non buffered
non cached

region 2 will be identical to region 0 in attributes, but will span the block of the default memory map designated "external ram". That would be the space for both SRAM and SDRAM or 0x6000 0000 to 0x9fff ffff.

finally
region 3 will be identical to region 1 in attributes, but will span the block of the default memory map designated "external devices". That would be span 0xa000 0000 to 0xdfff ffff

I needed to do this because the default memory map on the lpc1778 will allow read and write access to SDRAM block but not execution (code loading).
Worked out most of the details on paper and code will be in IE_egwu_setup.c. Here is a snippet below

    #define     EGWU_MPU_REGION_0_BASE          0x00000000
    #define     EGWU_MPU_REGION_0_ATTR          0x0302003B

    #define     EGWU_MPU_REGION_1_BASE          0x40000000
    #define     EGWU_MPU_REGION_1_ATTR          0x13040039

    #define     EGWU_MPU_REGION_2_BASE          0x60000000
    #define     EGWU_MPU_REGION_2_ATTR          0x0302003B

    #define     EGWU_MPU_REGION_3_BASE          0x40000000
    #define     EGWU_MPU_REGION_3_ATTR          0x1304003D

/*
 *****************************************************************
 *description:  configure the memory protection unit
 *              
 *note:         of the 8 regions I will setup 4 as below. regions
 *              0 and 2 are identical in attributes are as regions
 *              1 and 3
 *
 *              executable ram attributes:
 *              0000 0011 0000 0010 0000 0000 0011 1011
 *              peripheral device attributes:
 *              0001 0011 0000 0100 0000 0000 0011 1101
 *
 *              region 0 = internal ram (0x0000 0000 - 0x4000 0000)
 *                         strongly ordered, cache, executable
 *
 *              region 1 = int periphs  (0x4000 0000 - 0x6000 0000)
 *                         strongly ordered, non execute, non cache
 *
 *              region 2 = external ram (0x6000 0000 - 0xa000 0000)
 *                         strongly ordered, cache, executable
 *
 *              region 3 = ext periphes (0xa000 0000 - 0xf000 0000)
 *                         strongly ordered, non execute, non cache
 *
 *              disable interrupts while doing this
 *              and
 *              execute "dsb" and "isb" before exiting
 *****************************************************************
 */
void
setup_mpu(void)
{
    volatile unsigned int wdTemp, wdCount;
 
    wdTemp   = MPU->TYPE;
    wdTemp  &= MPU_TYPE_DREGION_Msk;
    wdTemp >>= MPU_TYPE_DREGION_Pos;
    if(wdTemp != 8)
        return;
    else
        {
        asm("cpsid i");
        MPU->CTRL = 0;
        }

    for(wdCount = 0; wdCount < 8; wdCount++)
        {
        MPU->RNR = wdCount;
        switch(wdCount)
                {
                case    0:
                        {
                        wdTemp = (EGWU_MPU_REGION_0_BASE & MPU_RBAR_ADDR_Msk);  
                        MPU->RBAR = wdTemp;
                        MPU->RASR = EGWU_MPU_REGION_0_ATTR;
                        break;
                        }
                case    1:
                        {
                        wdTemp = (EGWU_MPU_REGION_1_BASE & MPU_RBAR_ADDR_Msk);  
                        MPU->RBAR = wdTemp;
                        MPU->RASR = EGWU_MPU_REGION_1_ATTR;
                        break;
                        }
                case    2:
                        {
                        wdTemp = (EGWU_MPU_REGION_2_BASE & MPU_RBAR_ADDR_Msk);  
                        MPU->RBAR = wdTemp;
                        MPU->RASR = EGWU_MPU_REGION_2_ATTR;
                        break;
                        }
                case    3:
                        {
                        wdTemp = (EGWU_MPU_REGION_3_BASE & MPU_RBAR_ADDR_Msk);  
                        MPU->RBAR = wdTemp;
                        MPU->RASR = EGWU_MPU_REGION_3_ATTR;
                        break;
                        }
                default:
                        break;
                }
        }

    MPU->CTRL = MPU_CTRL_ENABLE_Msk;
    asm("isb");
    asm("dsb");
    asm("cpsie i");
}