/*
**********************************************************************
*name: IE_stm32_dma.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_dma header
**********************************************************************
*/
#ifndef IE_STM32_DMA
#define IE_STM32_DMA
#define PTR_STM32_DMA1_BASE 0x40020000
#define PTR_STM32_DMA2_BASE 0x40020400
/*
**********************************************************************
*dma interrupt status register
**********************************************************************
*/
#define PTR_STM32_DMA1_ISR (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 0)
#define PTR_STM32_DMA2_ISR (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 0)
#define STM32_DMA_ISR_TEIF_MASK 0x8888888
#define STM32_DMA_ISR_HTIF_MASK 0x4444444
#define STM32_DMA_ISR_TCIF_MASK 0x2222222
#define STM32_DMA_ISR_GIF_MASK 0x1111111
/*
**********************************************************************
*dma interrupt flag clear register
**********************************************************************
*/
#define PTR_STM32_DMA1_IFCR (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 4)
#define PTR_STM32_DMA2_IFCR (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 4)
#define STM32_DMA_IFCR_CTEIF_MASK 0x8888888
#define STM32_DMA_IFCR_CHTIF_MASK 0x4444444
#define STM32_DMA_IFCR_CTCIF_MASK 0x2222222
#define STM32_DMA_IFCR_CGIF_MASK 0x1111111
/*
**********************************************************************
*dma channel x configuration register
**********************************************************************
*/
#define PTR_STM32_DMA1_CCR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 8)
#define PTR_STM32_DMA1_CCR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 28)
#define PTR_STM32_DMA1_CCR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 48)
#define PTR_STM32_DMA1_CCR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 68)
#define PTR_STM32_DMA1_CCR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 88)
#define PTR_STM32_DMA1_CCR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 108)
#define PTR_STM32_DMA1_CCR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 128)
#define PTR_STM32_DMA2_CCR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 8)
#define PTR_STM32_DMA2_CCR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 28)
#define PTR_STM32_DMA2_CCR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 48)
#define PTR_STM32_DMA2_CCR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 68)
#define PTR_STM32_DMA2_CCR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 88)
#define STM32_DMA_CCR_MEM2MEM_ENABLED (1 << 14)
#define STM32_DMA_CCR_PL_OFFSET 12
#define STM32_DMA_CCR_PL_MASK 0x3
#define STM32_DMA_CCR_PL_LOW (0 << 12)
#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
#define STM32_DMA_CCR_PL_HIGH (2 << 12)
#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
#define STM32_DMA_CCR_MSIZE_OFFSET 10
#define STM32_DMA_CCR_MSIZE_MASK 0x3
#define STM32_DMA_CCR_MSIZE_8 (0 << 10)
#define STM32_DMA_CCR_MSIZE_16 (1 << 10)
#define STM32_DMA_CCR_MSIZE_32 (2 << 10)
#define STM32_DMA_CCR_PSIZE_OFFSET 8
#define STM32_DMA_CCR_PSIZE_MASK 0x3
#define STM32_DMA_CCR_PSIZE_8 (0 << 8)
#define STM32_DMA_CCR_PSIZE_16 (1 << 8)
#define STM32_DMA_CCR_PSIZE_32 (2 << 8)
#define STM32_DMA_CCR_MINC (1 << 7)
#define STM32_DMA_CCR_PINC (1 << 6)
#define STM32_DMA_CCR_CIRC (1 << 5)
#define STM32_DMA_CCR_DIR_FROM_PERIPHERAL (0 << 4)
#define STM32_DMA_CCR_DIR_FROM_MEMORY (1 << 4)
#define STM32_DMA_CCR_TEIE (1 << 3)
#define STM32_DMA_CCR_HTIE (1 << 2)
#define STM32_DMA_CCR_TCIE (1 << 1)
#define STM32_DMA_CCR_EN (1 << 0)
/*
**********************************************************************
*dma channel x number of data register
**********************************************************************
*/
#define PTR_STM32_DMA1_CNDTR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 12)
#define PTR_STM32_DMA1_CNDTR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 32)
#define PTR_STM32_DMA1_CNDTR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 52)
#define PTR_STM32_DMA1_CNDTR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 72)
#define PTR_STM32_DMA1_CNDTR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 92)
#define PTR_STM32_DMA1_CNDTR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 112)
#define PTR_STM32_DMA1_CNDTR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 132)
#define PTR_STM32_DMA2_CNDTR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 12)
#define PTR_STM32_DMA2_CNDTR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 32)
#define PTR_STM32_DMA2_CNDTR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 52)
#define PTR_STM32_DMA2_CNDTR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 72)
#define PTR_STM32_DMA2_CNDTR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 92)
#define STM32_DMA_CNDTR_MASK 0x0ffff
/*
**********************************************************************
*dma channel x peripheral address register
**********************************************************************
*/
#define PTR_STM32_DMA1_CPAR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 16)
#define PTR_STM32_DMA1_CPAR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 36)
#define PTR_STM32_DMA1_CPAR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 56)
#define PTR_STM32_DMA1_CPAR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 76)
#define PTR_STM32_DMA1_CPAR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 96)
#define PTR_STM32_DMA1_CPAR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 116)
#define PTR_STM32_DMA1_CPAR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 136)
#define PTR_STM32_DMA2_CPAR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 16)
#define PTR_STM32_DMA2_CPAR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 36)
#define PTR_STM32_DMA2_CPAR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 56)
#define PTR_STM32_DMA2_CPAR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 76)
#define PTR_STM32_DMA2_CPAR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 96)
/*
**********************************************************************
*dma channel x memory address register
**********************************************************************
*/
#define PTR_STM32_DMA1_CMAR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 20)
#define PTR_STM32_DMA1_CMAR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 40)
#define PTR_STM32_DMA1_CMAR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 60)
#define PTR_STM32_DMA1_CMAR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 80)
#define PTR_STM32_DMA1_CMAR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 100)
#define PTR_STM32_DMA1_CMAR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 120)
#define PTR_STM32_DMA1_CMAR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 140)
#define PTR_STM32_DMA2_CMAR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 20)
#define PTR_STM32_DMA2_CMAR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 40)
#define PTR_STM32_DMA2_CMAR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 60)
#define PTR_STM32_DMA2_CMAR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 80)
#define PTR_STM32_DMA2_CMAR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 100)
#endif
Monday, July 29, 2013
IE_stm32_dma.h
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