Phase 2: my script files for openocd 0.9.0

alias openocd_ftdi='openocd -s /home/rombios/DEVEL/EGWU/openocd/scripts -f interface/ftdi/egwu_interface_usb.cfg -f board/egwu_board.cfg'
alias openocd_olimex='openocd -s /home/rombios/DEVEL/EGWU/openocd/scripts -f interface/ftdi/olimex-jtag-tiny.cfg -f board/egwu_board.cfg'
alias openocd_jlink='openocd -f interface/jlink.cfg -f board/olimex_stm32_h103.cfg'

# egwu_board.cfg

set WORKAREASIZE 0x10000
source [find target/egwu_target_1788.cfg] 

#
# embedded projects openocd usb adapter v3
# egwu_interface_usb.cfg (ftdi)
# http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=14
#

interface               ftdi
ftdi_vid_pid            0x0403 0x6010
ftdi_channel            0
#ftdi_layout_init       0x1000 0x3d1b
#working ftdi_layout_init       0x0008 0x000b
#ftdi_layout_init       0x1000 0x3d0b

ftdi_layout_init        0x0008 0x000b
ftdi_layout_signal      nTRST -data 0x0010

# egwu_target_1788.cfg

set CHIPNAME    lpc1788
set CPUTAPID    0x4ba00477
set CPURAMSIZE  0x10000
set CPUROMSIZE  0x80000

# CCLK is the core clock frequency in KHz

set CCLK 120000
source [find target/egwu_target_17xx.cfg];
#cortex_m reset_config sysresetreq
cortex_m reset_config trst_only 

# egwu_target_17xx.cfg

adapter_khz 2000

if { [info exists CHIPNAME] } {
        set _CHIPNAME $CHIPNAME
} else {
        error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
if { [info exists CCLK] } {
        set _CCLK $CCLK
} else {
        set _CCLK 24000
}

if { [info exists CPUTAPID] } {
        set _CPUTAPID $CPUTAPID
} else {
        error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

if { [info exists CPURAMSIZE] } {
  set _CPURAMSIZE $CPURAMSIZE
} else {
        error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

if { [info exists CPUROMSIZE] } {
  set _CPUROMSIZE $CPUROMSIZE
} else {
        error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME

# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE

# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code
# (including a boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
        lpc1700 $_CCLK calc_checksum

# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
#adapter_khz  250

# delays on reset lines
adapter_nsrst_assert_width      500
adapter_nsrst_delay             500

jtag_ntrst_assert_width         500
jtag_ntrst_delay                500

$_TARGETNAME configure -event reset-init {
        mww 0x400FC040 0x01
        mww 0xe000ed08 0x10000000
}

# perform a soft reset
#cortex_m reset_config sysresetreq
cortex_m reset_config trst_only