/*
**********************************************************************
*name: IE_stm32_usb.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_usb header
**********************************************************************
*/
#ifndef IE_STM32_USB
#define IE_STM32_USB
#define PTR_STM32_USB_BASE 0x40005c00
#define PTR_STM32_USB_EPRAM 0x40006000
/*
**********************************************************************
*usb base address
**********************************************************************
*/
#define PTR_STM32_USB_BTABLE (volatile unsigned int *)(PTR_STM32_USB_BASE + 80)
/*
**********************************************************************
*usb control register
**********************************************************************
*/
#define PTR_STM32_USB_CNTR (volatile unsigned int *)(PTR_STM32_USB_BASE + 64)
#define STM32_USB_CNTR_CTRM (1 << 15)
#define STM32_USB_CNTR_PMAOVRM (1 << 14)
#define STM32_USB_CNTR_ERRM (1 << 13)
#define STM32_USB_CNTR_WKUPM (1 << 12)
#define STM32_USB_CNTR_SUSPM (1 << 11)
#define STM32_USB_CNTR_RESETM (1 << 10)
#define STM32_USB_CNTR_SOFM (1 << 9)
#define STM32_USB_CNTR_ESOFM (1 << 8)
#define STM32_USB_CNTR_RESUME (1 << 4)
#define STM32_USB_CNTR_FSUSP (1 << 3)
#define STM32_USB_CNTR_LP_MODE (1 << 2)
#define STM32_USB_CNTR_PDWN (1 << 1)
#define STM32_USB_CNTR_FRES (1 << 0)
/*
**********************************************************************
*usb interrupt status register
**********************************************************************
*/
#define PTR_STM32_USB_ISTR (volatile unsigned int *)(PTR_STM32_USB_BASE + 68)
#define STM32_USB_ISTR_CTR (1 << 15)
#define STM32_USB_ISTR_PMAOVR (1 << 14)
#define STM32_USB_ISTR_ERR (1 << 13)
#define STM32_USB_ISTR_WKUP (1 << 12)
#define STM32_USB_ISTR_SUSP (1 << 11)
#define STM32_USB_ISTR_RESET (1 << 10)
#define STM32_USB_ISTR_SOF (1 << 9)
#define STM32_USB_ISTR_ESOF (1 << 8)
#define STM32_USB_ISTR_DIR_MASK (1 << 4)
#define STM32_USB_ISTR_DIR_IN (0 << 4)
#define STM32_USB_ISTR_DIR_OUT (1 << 4)
#define STM32_USB_ISTR_EP_ID_OFFSET 0
#define STM32_USB_ISTR_EP_ID_MASK (0x0f << 0)
/*
**********************************************************************
*usb interrupt status register
**********************************************************************
*/
#define PTR_STM32_USB_FNR (volatile unsigned int *)(PTR_STM32_USB_BASE + 72)
#define STM32_USB_FNR_RXDP (1 << 15)
#define STM32_USB_FNR_RXDM (1 << 14)
#define STM32_USB_FNR_LCK (1 << 13)
#define STM32_USB_FNR_LSOF_OFFSET 11
#define STM32_USB_FNR_LSOF_MASK (0x3 << 11)
#define STM32_USB_FNR_FN_OFFSET 0
#define STM32_USB_FNR_FN_MASK (0x7ff << 0)
/*
**********************************************************************
*usb device address register
**********************************************************************
*/
#define PTR_STM32_USB_DADDR (volatile unsigned int *)(PTR_STM32_USB_BASE + 76)
#define STM32_USB_DADDR_EF (1 << 7)
#define STM32_USB_DADDR_ADD_OFFSET 0
#define STM32_USB_DADDR_ADD_MASK (0x7f << 0)
/*
**********************************************************************
*usb endpoint specific register
**********************************************************************
*/
#define PTR_STM32_USB_EP0R (volatile unsigned int *)(PTR_STM32_USB_BASE + 0)
#define PTR_STM32_USB_EP1R (volatile unsigned int *)(PTR_STM32_USB_BASE + 4)
#define PTR_STM32_USB_EP2R (volatile unsigned int *)(PTR_STM32_USB_BASE + 8)
#define PTR_STM32_USB_EP3R (volatile unsigned int *)(PTR_STM32_USB_BASE + 12)
#define PTR_STM32_USB_EP4R (volatile unsigned int *)(PTR_STM32_USB_BASE + 16)
#define PTR_STM32_USB_EP5R (volatile unsigned int *)(PTR_STM32_USB_BASE + 20)
#define PTR_STM32_USB_EP6R (volatile unsigned int *)(PTR_STM32_USB_BASE + 24)
#define PTR_STM32_USB_EP7R (volatile unsigned int *)(PTR_STM32_USB_BASE + 28)
#define STM32_USB_EPR_CTR_RX (1 << 15)
#define STM32_USB_EPR_DTOG_RX (1 << 14)
#define STM32_USB_EPR_DTOG_RX_OFFSET 14
#define STM32_USB_EPR_STAT_RX_OFFSET 12
#define STM32_USB_EPR_STAT_RX_MASK (0x3 << 12)
#define STM32_USB_EPR_STAT_RX_DISABLE 0
#define STM32_USB_EPR_STAT_RX_STALL 1
#define STM32_USB_EPR_STAT_RX_NAK 2
#define STM32_USB_EPR_STAT_RX_VALID 3
#define STM32_USB_EPR_SETUP (1 << 11)
#define STM32_USB_EPR_EP_TYPE_OFFSET 9
#define STM32_USB_EPR_EP_TYPE_MASK (0x3 << 9)
#define STM32_USB_EPR_EP_TYPE_BULK 0
#define STM32_USB_EPR_EP_TYPE_CONTROL 1
#define STM32_USB_EPR_EP_TYPE_ISO 2
#define STM32_USB_EPR_EP_TYPE_INTERRUPT 3
#define STM32_USB_EPR_EP_KIND (1 << 8)
#define STM32_USB_EPR_CTR_TX (1 << 7)
#define STM32_USB_EPR_DTOG_TX (1 << 6)
#define STM32_USB_EPR_DTOG_TX_OFFSET 6
#define STM32_USB_EPR_STAT_TX_OFFSET 4
#define STM32_USB_EPR_STAT_TX_MASK (0x3 << 4)
#define STM32_USB_EPR_STAT_TX_DISABLE 0
#define STM32_USB_EPR_STAT_TX_STALL 1
#define STM32_USB_EPR_STAT_TX_NAK 2
#define STM32_USB_EPR_STAT_TX_VALID 3
#define STM32_USB_EPR_EA_OFFSET 0
#define STM32_USB_EPR_EA_MASK (0x0f << 0)
/*
**********************************************************************
*usb buffer description table. I can put the buffer description table
*anyway in the 512 memory I choose to put it in the beginning. this
*should be addressed as short (16 bits)
*
*transmission buffer address n
**********************************************************************
*/
#define PTR_STM32_USB_ADDR0_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 0)
#define PTR_STM32_USB_ADDR1_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 8)
#define PTR_STM32_USB_ADDR2_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 16)
#define PTR_STM32_USB_ADDR3_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 24)
#define PTR_STM32_USB_ADDR4_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 32)
#define PTR_STM32_USB_ADDR5_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 40)
#define PTR_STM32_USB_ADDR6_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 48)
#define PTR_STM32_USB_ADDR7_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 56)
#define STM32_USB_ADDR_TX_OFFSET 1
#define STM32_USB_ADDR_TX_MASK (0x7fff << 1)
/*
**********************************************************************
*transmission byte count n
**********************************************************************
*/
#define PTR_STM32_USB_COUNT0_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 2)
#define PTR_STM32_USB_COUNT1_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 10)
#define PTR_STM32_USB_COUNT2_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 18)
#define PTR_STM32_USB_COUNT3_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 26)
#define PTR_STM32_USB_COUNT4_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 34)
#define PTR_STM32_USB_COUNT5_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 42)
#define PTR_STM32_USB_COUNT6_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 50)
#define PTR_STM32_USB_COUNT7_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 58)
#define STM32_USB_COUNT_TX_OFFSET 0
#define STM32_USB_COUNT_TX_MASK (0x3ff << 0)
/*
**********************************************************************
*reception buffer address n
**********************************************************************
*/
#define PTR_STM32_USB_ADDR0_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 4)
#define PTR_STM32_USB_ADDR1_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 12)
#define PTR_STM32_USB_ADDR2_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 20)
#define PTR_STM32_USB_ADDR3_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 28)
#define PTR_STM32_USB_ADDR4_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 36)
#define PTR_STM32_USB_ADDR5_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 44)
#define PTR_STM32_USB_ADDR6_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 52)
#define PTR_STM32_USB_ADDR7_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 60)
#define STM32_USB_ADDR_RX_OFFSET 1
#define STM32_USB_ADDR_RX_MASK (0x7fff << 1)
/*
**********************************************************************
*reception byte count n
**********************************************************************
*/
#define PTR_STM32_USB_COUNT0_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 6)
#define PTR_STM32_USB_COUNT1_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 14)
#define PTR_STM32_USB_COUNT2_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 22)
#define PTR_STM32_USB_COUNT3_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 30)
#define PTR_STM32_USB_COUNT4_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 38)
#define PTR_STM32_USB_COUNT5_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 46)
#define PTR_STM32_USB_COUNT6_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 54)
#define PTR_STM32_USB_COUNT7_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 62)
#define STM32_USB_COUNT_RX_BL_SIZE_MASK (1 << 15)
#define STM32_USB_COUNT_RX_BL_SIZE_2BYTE (0 << 15)
#define STM32_USB_COUNT_RX_BL_SIZE_32BYTE (1 << 15)
#define STM32_USB_COUNT_RX_NUM_BLOCK_OFFSET 10
#define STM32_USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << 10)
#define STM32_USB_COUNT_RX_OFFSET 0
#define STM32_USB_COUNT_RX_MASK (0x3ff << 0)
/*
**********************************************************************
*module routines
**********************************************************************
*/
void stm32_usb_init(void);
void stm32_usb_pre_reset_setup(unsigned int wdEndPNum,\
unsigned int wdEndPType,\
unsigned int wdEndPSize);
void stm32_usb_post_reset_setup(unsigned int wdEndPNum,\
unsigned int wdEndPType,\
unsigned int wdEndPSize);
int stm32_usb_endp_send_packet(unsigned int wdEndPNum,\
unsigned char *ptrBuffer,\
unsigned int wdEndPSize,\
unsigned int wdBytelen);
int stm32_usb_build_endp_descriptors(unsigned int wdEndPNum,\
unsigned int wdEndPType,\
unsigned int wdEndPSize,\
unsigned int *ptrDescAddr,\
unsigned int wdLclPktAddr);
int stm32_usb_endp_get_packet(unsigned int wdEndPNum,\
unsigned char *ptrBuffer,\
unsigned int wdBytelen);
void stm32_usb_connect_pullup(unsigned int wdPin);
void stm32_usb_disconnect_pullup(unsigned int wdPin);
#endif
Thursday, July 18, 2013
IE_stm32_usb.h
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