/*
**********************************************************************
*name: IE_stm32_rstcc.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_rstcc header
**********************************************************************
*/
#ifndef IE_STM32_RSTCC
#define IE_STM32_RSTCC
#define PTR_STM32_RCC_BASE 0x40021000
/*
**********************************************************************
*clock control register
**********************************************************************
*/
#define PTR_STM32_RCC_CR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 0)
#define STM32_RCC_CR_PLLRDY (1 << 25)
#define STM32_RCC_CR_PLLON (1 << 24)
#define STM32_RCC_CR_CSSON (1 << 19)
#define STM32_RCC_CR_HSEBYP (1 << 18)
#define STM32_RCC_CR_HSERDY (1 << 17)
#define STM32_RCC_CR_HSEON (1 << 16)
#define STM32_RCC_CR_HSICAL_OFFSET 8
#define STM32_RCC_CR_HSICAL_MASK (0x0ff << 8)
#define STM32_RCC_CR_HSITRIM_OFFSET 3
#define STM32_RCC_CR_HSITRIM_MASK (0x1f << 3)
#define STM32_RCC_CR_HSIRDY (1 << 1)
#define STM32_RCC_CR_HSION (1 << 0)
/*
**********************************************************************
*clock configuration register
**********************************************************************
*/
#define PTR_STM32_RCC_CFGR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 4)
#define STM32_RCC_CFGR_MCO_OFFSET 24
#define STM32_RCC_CFGR_MCO_MASK (0x7 << 24)
#define STM32_RCC_CFGR_MCO_NOCLK (0 << 24)
#define STM32_RCC_CFGR_MCO_SYSCLK (4 << 24)
#define STM32_RCC_CFGR_MCO_HSI (5 << 24)
#define STM32_RCC_CFGR_MCO_HSE (6 << 24)
#define STM32_RCC_CFGR_MCO_PLL (7 << 24)
#define STM32_RCC_CFGR_USBPRE (1 << 22)
#define STM32_RCC_CFGR_PLLMUL_OFFSET 18
#define STM32_RCC_CFGR_PLLMUL_MASK (0x0f << 18)
#define STM32_RCC_CFGR_PLLMUL_ADJUSTMENT 2
#define STM32_RCC_CFGR_PLLXTPRE (1 << 17)
#define STM32_RCC_CFGR_PLLSRC (1 << 16)
#define STM32_RCC_CFGR_ADCPRE_OFFSET 14
#define STM32_RCC_CFGR_ADCPRE_MASK (0x3 << 14)
#define STM32_RCC_CFGR_ADCPRE_BY_2 0
#define STM32_RCC_CFGR_ADCPRE_BY_4 1
#define STM32_RCC_CFGR_ADCPRE_BY_6 2
#define STM32_RCC_CFGR_ADCPRE_BY_8 3
#define STM32_RCC_CFGR_PPRE2_OFFSET 11
#define STM32_RCC_CFGR_PPRE2_MASK (0x7 << 11)
#define STM32_RCC_CFGR_PPRE2_NODIV 0
#define STM32_RCC_CFGR_PPRE2_BY_2 4
#define STM32_RCC_CFGR_PPRE2_BY_4 5
#define STM32_RCC_CFGR_PPRE2_BY_8 6
#define STM32_RCC_CFGR_PPRE2_BY_16 7
#define STM32_RCC_CFGR_PPRE1_OFFSET 8
#define STM32_RCC_CFGR_PPRE1_MASK (0x7 << 8)
#define STM32_RCC_CFGR_PPRE1_NODIV 0
#define STM32_RCC_CFGR_PPRE1_2 4
#define STM32_RCC_CFGR_PPRE1_4 5
#define STM32_RCC_CFGR_PPRE1_8 6
#define STM32_RCC_CFGR_PPRE1_16 7
#define STM32_RCC_CFGR_HPRE_OFFSET 4
#define STM32_RCC_CFGR_HPRE_MASK (0x0f << 4)
#define STM32_RCC_CFGR_HPRE_NODIV 0
#define STM32_RCC_CFGR_HPRE_BY_2 9
#define STM32_RCC_CFGR_HPRE_BY_4 10
#define STM32_RCC_CFGR_HPRE_BY_16 11
#define STM32_RCC_CFGR_HPRE_BY_64 12
#define STM32_RCC_CFGR_HPRE_BY_128 13
#define STM32_RCC_CFGR_HPRE_BY_256 14
#define STM32_RCC_CFGR_HPRE_BY_512 15
#define STM32_RCC_CFGR_SWS_OFFSET 2
#define STM32_RCC_CFGR_SWS_MASK (0x3 << 2)
#define STM32_RCC_CFGR_SWS_HSI 0
#define STM32_RCC_CFGR_SWS_HSE 1
#define STM32_RCC_CFGR_SWS_PLL 2
#define STM32_RCC_CFGR_SW_OFFSET 0
#define STM32_RCC_CFGR_SW_MASK (0x3 << 0)
#define STM32_RCC_CFGR_SW_HSI 0
#define STM32_RCC_CFGR_SW_HSE 1
#define STM32_RCC_CFGR_SW_PLL 2
/*
**********************************************************************
*clock interrupt register
**********************************************************************
*/
#define PTR_STM32_RCC_CIR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 8)
#define STM32_RCC_CIR_CSSC (1 << 24)
#define STM32_RCC_CIR_PLLRDYC (1 << 20)
#define STM32_RCC_CIR_HSERDYC (1 << 19)
#define STM32_RCC_CIR_HSIRDYC (1 << 18)
#define STM32_RCC_CIR_LSERDYC (1 << 17)
#define STM32_RCC_CIR_LSIRDYC (1 << 16)
#define STM32_RCC_CIR_PLLRDYIE (1 << 12)
#define STM32_RCC_CIR_HSERDYIE (1 << 11)
#define STM32_RCC_CIR_HSIRDYIE (1 << 10)
#define STM32_RCC_CIR_LSERDYIE (1 << 9)
#define STM32_RCC_CIR_LSIRDYIE (1 << 8)
#define STM32_RCC_CIR_CSSF (1 << 7)
#define STM32_RCC_CIR_PLLRDYF (1 << 4)
#define STM32_RCC_CIR_HSERDYF (1 << 3)
#define STM32_RCC_CIR_HSIRDYF (1 << 2)
#define STM32_RCC_CIR_LSERDYF (1 << 1)
#define STM32_RCC_CIR_LSIRDYF (1 << 0)
/*
**********************************************************************
*apb2 peripheral reset register
**********************************************************************
*/
#define PTR_STM32_RCC_APB2RSTR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 12)
#define STM32_RCC_APB2RSTR_TIM11RST (1 << 21)
#define STM32_RCC_APB2RSTR_TIM10RST (1 << 20)
#define STM32_RCC_APB2RSTR_TIM9RST (1 << 19)
#define STM32_RCC_APB2RSTR_ADC3RST (1 << 15)
#define STM32_RCC_APB2RSTR_UART1RST (1 << 14)
#define STM32_RCC_APB2RSTR_TIM8RST (1 << 13)
#define STM32_RCC_APB2RSTR_SPI1RST (1 << 12)
#define STM32_RCC_APB2RSTR_TIM1RST (1 << 11)
#define STM32_RCC_APB2RSTR_ADC2RST (1 << 10)
#define STM32_RCC_APB2RSTR_ADC1RST (1 << 9)
#define STM32_RCC_APB2RSTR_IOPGRST (1 << 8)
#define STM32_RCC_APB2RSTR_IOPFRST (1 << 7)
#define STM32_RCC_APB2RSTR_IOPERST (1 << 6)
#define STM32_RCC_APB2RSTR_IOPDRST (1 << 5)
#define STM32_RCC_APB2RSTR_IOPCRST (1 << 4)
#define STM32_RCC_APB2RSTR_IOPBRST (1 << 3)
#define STM32_RCC_APB2RSTR_IOPARST (1 << 2)
#define STM32_RCC_APB2RSTR_AFIORST (1 << 0)
/*
**********************************************************************
*apb1 peripheral reset register
**********************************************************************
*/
#define PTR_STM32_RCC_APB1RSTR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 16)
#define STM32_RCC_APB1RSTR_DACRST (1 << 29)
#define STM32_RCC_APB1RSTR_PWRRST (1 << 28)
#define STM32_RCC_APB1RSTR_BKPRST (1 << 27)
#define STM32_RCC_APB1RSTR_CANRST (1 << 25)
#define STM32_RCC_APB1RSTR_USBRST (1 << 23)
#define STM32_RCC_APB1RSTR_I2C2RST (1 << 22)
#define STM32_RCC_APB1RSTR_I2C1RST (1 << 21)
#define STM32_RCC_APB1RSTR_UART5RST (1 << 20)
#define STM32_RCC_APB1RSTR_UART4RST (1 << 19)
#define STM32_RCC_APB1RSTR_UART3RST (1 << 18)
#define STM32_RCC_APB1RSTR_UART2RST (1 << 17)
#define STM32_RCC_APB1RSTR_SPI3RST (1 << 15)
#define STM32_RCC_APB1RSTR_SPI2RST (1 << 14)
#define STM32_RCC_APB1RSTR_WWDGRST (1 << 11)
#define STM32_RCC_APB1RSTR_TIM14RST (1 << 8)
#define STM32_RCC_APB1RSTR_TIM13RST (1 << 7)
#define STM32_RCC_APB1RSTR_TIM12RST (1 << 6)
#define STM32_RCC_APB1RSTR_TIM7RST (1 << 5)
#define STM32_RCC_APB1RSTR_TIM6RST (1 << 4)
#define STM32_RCC_APB1RSTR_TIM5RST (1 << 3)
#define STM32_RCC_APB1RSTR_TIM4RST (1 << 2)
#define STM32_RCC_APB1RSTR_TIM3RST (1 << 1)
#define STM32_RCC_APB1RSTR_TIM2RST (1 << 0)
/*
**********************************************************************
*ahb peripheral clock enable register
**********************************************************************
*/
#define PTR_STM32_RCC_AHBENR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 20)
#define STM32_RCC_AHBENR_SDIOEN (1 << 10)
#define STM32_RCC_AHBENR_FSMCEN (1 << 8)
#define STM32_RCC_AHBENR_CRCEN (1 << 6)
#define STM32_RCC_AHBENR_FLITFEN (1 << 4)
#define STM32_RCC_AHBENR_SRAMEN (1 << 2)
#define STM32_RCC_AHBENR_DMA2EN (1 << 1)
#define STM32_RCC_AHBENR_DMA1EN (1 << 0)
/*
**********************************************************************
*apb2 peripheral clock enable register
**********************************************************************
*/
#define PTR_STM32_RCC_APB2ENR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 24)
#define STM32_RCC_APB2ENR_TIM11EN (1 << 21)
#define STM32_RCC_APB2ENR_TIM10EN (1 << 20)
#define STM32_RCC_APB2ENR_TIM9EN (1 << 19)
#define STM32_RCC_APB2ENR_ADC3EN (1 << 15)
#define STM32_RCC_APB2ENR_UART1EN (1 << 14)
#define STM32_RCC_APB2ENR_TIM8EN (1 << 13)
#define STM32_RCC_APB2ENR_SPI1EN (1 << 12)
#define STM32_RCC_APB2ENR_TIM1EN (1 << 11)
#define STM32_RCC_APB2ENR_ADC2EN (1 << 10)
#define STM32_RCC_APB2ENR_ADC1EN (1 << 9)
#define STM32_RCC_APB2ENR_IOPGEN (1 << 8)
#define STM32_RCC_APB2ENR_IOPFEN (1 << 7)
#define STM32_RCC_APB2ENR_IOPEEN (1 << 6)
#define STM32_RCC_APB2ENR_IOPDEN (1 << 5)
#define STM32_RCC_APB2ENR_IOPCEN (1 << 4)
#define STM32_RCC_APB2ENR_IOPBEN (1 << 3)
#define STM32_RCC_APB2ENR_IOPAEN (1 << 2)
#define STM32_RCC_APB2ENR_AFIOEN (1 << 0)
/*
**********************************************************************
*apb1 peripheral clock enable register
**********************************************************************
*/
#define PTR_STM32_RCC_APB1ENR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 28)
#define STM32_RCC_APB1ENR_DACEN (1 << 29)
#define STM32_RCC_APB1ENR_PWREN (1 << 28)
#define STM32_RCC_APB1ENR_BKPEN (1 << 27)
#define STM32_RCC_APB1ENR_CANEN (1 << 25)
#define STM32_RCC_APB1ENR_USBEN (1 << 23)
#define STM32_RCC_APB1ENR_I2C2EN (1 << 22)
#define STM32_RCC_APB1ENR_I2C1EN (1 << 21)
#define STM32_RCC_APB1ENR_UART5EN (1 << 20)
#define STM32_RCC_APB1ENR_UART4EN (1 << 19)
#define STM32_RCC_APB1ENR_UART3EN (1 << 18)
#define STM32_RCC_APB1ENR_UART2EN (1 << 17)
#define STM32_RCC_APB1ENR_SPI3EN (1 << 15)
#define STM32_RCC_APB1ENR_SPI2EN (1 << 14)
#define STM32_RCC_APB1ENR_WWDGEN (1 << 11)
#define STM32_RCC_APB1ENR_TIM14EN (1 << 8)
#define STM32_RCC_APB1ENR_TIM13EN (1 << 7)
#define STM32_RCC_APB1ENR_TIM12EN (1 << 6)
#define STM32_RCC_APB1ENR_TIM7EN (1 << 5)
#define STM32_RCC_APB1ENR_TIM6EN (1 << 4)
#define STM32_RCC_APB1ENR_TIM5EN (1 << 3)
#define STM32_RCC_APB1ENR_TIM4EN (1 << 2)
#define STM32_RCC_APB1ENR_TIM3EN (1 << 1)
#define STM32_RCC_APB1ENR_TIM2EN (1 << 0)
/*
**********************************************************************
*backup domain control register
**********************************************************************
*/
#define PTR_STM32_RCC_BDCR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 32)
#define STM32_RCC_BDCR_BDRST (1 << 16)
#define STM32_RCC_BDCR_RTCEN (1 << 15)
#define STM32_RCC_BDCR_RTCSEL_OFFSET 8
#define STM32_RCC_BDCR_RTCSEL_MASK (0x3 << 8)
#define STM32_RCC_BDCR_RTCSEL_NOCLK 0
#define STM32_RCC_BDCR_RTCSEL_LSE 1
#define STM32_RCC_BDCR_RTCSEL_HSE 3
#define STM32_RCC_BDCR_LSEBYP (1 << 2)
#define STM32_RCC_BDCR_LSERDY (1 << 1)
#define STM32_RCC_BDCR_LSEON (1 << 0)
/*
**********************************************************************
*control/status register
**********************************************************************
*/
#define PTR_STM32_RCC_CSR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 36)
#define STM32_RCC_CSR_LPWRRSTF (1 << 31)
#define STM32_RCC_CSR_WWDGRSTF (1 << 30)
#define STM32_RCC_CSR_IWDGRSTF (1 << 29)
#define STM32_RCC_CSR_SETRSTF (1 << 28)
#define STM32_RCC_CSR_PORRSTF (1 << 27)
#define STM32_RCC_CSR_PINRSTF (1 << 26)
#define STM32_RCC_CSR_RMVF (1 << 24)
#define STM32_RCC_CSR_LSIRDY (1 << 1)
#define STM32_RCC_CSR_LSION (1 << 0)
#endif
Thursday, July 18, 2013
IE_stm32_rstcc.h
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