IE_stm32_gpio.h

/*
 **********************************************************************
 *name:         IE_stm32_gpio.h
 *author:       Samuel Igwe
 *date:         07/16/2013
 *description:  Igbo Embedded stm32_gpio header
 **********************************************************************
 */
#ifndef IE_STM32_GPIO
#define IE_STM32_GPIO


#define PTR_STM32_GPIO_A_BASE                           0x40010800 
#define PTR_STM32_GPIO_B_BASE                           0x40010c00 
#define PTR_STM32_GPIO_C_BASE                           0x40011000 
#define PTR_STM32_GPIO_D_BASE                           0x40011400 



/*
 **********************************************************************
 *port configuration #defines
 **********************************************************************
 */
#define STM32_GPIO_CNF0_OFFSET                          2
        #define STM32_GPIO_CNF_MASK                     3
        #define STM32_GPIO_CNF_IN_ANALOG                0
        #define STM32_GPIO_CNF_IN_FLOATING              1
        #define STM32_GPIO_CNF_IN_PULL_UP_DOWN          2

        #define STM32_GPIO_CNF_OUT_GEN_PUSH_PULL        0
        #define STM32_GPIO_CNF_OUT_GEN_OPEN_DRAIN       1
        #define STM32_GPIO_CNF_OUT_ALT_PUSH_PULL        2
        #define STM32_GPIO_CNF_OUT_ALT_OPEN_DRAIN       3



#define STM32_GPIO_MODE1_OFFSET                         4
        #define STM32_GPIO_MODE_INPUT_MODE              0
        #define STM32_GPIO_MODE_OUTPUT_10MHZ            1
        #define STM32_GPIO_MODE_OUTPUT_2MHZ             2
        #define STM32_GPIO_MODE_OUTPUT_50MHZ            3



/*
 **********************************************************************
 *port configuration register low
 **********************************************************************
 */
#define PTR_STM32_GPIO_A_CRL    (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 0)
#define PTR_STM32_GPIO_B_CRL    (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 0)
#define PTR_STM32_GPIO_C_CRL    (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 0)
#define PTR_STM32_GPIO_D_CRL    (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 0)



/*
 **********************************************************************
 *port configuration register high
 **********************************************************************
 */
#define PTR_STM32_GPIO_A_CRH    (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 4)
#define PTR_STM32_GPIO_B_CRH    (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 4)
#define PTR_STM32_GPIO_C_CRH    (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 4)
#define PTR_STM32_GPIO_D_CRH    (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 4)



/*
 **********************************************************************
 *port input data register
 **********************************************************************
 */
#define PTR_STM32_GPIO_A_IDR    (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 8)
#define PTR_STM32_GPIO_B_IDR    (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 8)
#define PTR_STM32_GPIO_C_IDR    (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 8)
#define PTR_STM32_GPIO_D_IDR    (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 8)
        #define STM32_GPIO_IDR_MASK                     0x0ffff



/*
 **********************************************************************
 *port output data register
 **********************************************************************
 */
#define PTR_STM32_GPIO_A_ODR    (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 12)
#define PTR_STM32_GPIO_B_ODR    (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 12)
#define PTR_STM32_GPIO_C_ODR    (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 12)
#define PTR_STM32_GPIO_D_ODR    (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 12)
        #define STM32_GPIO_ODR_MASK                     0x0ffff



/*
 **********************************************************************
 *port bit set/reset register
 **********************************************************************
 */
#define PTR_STM32_GPIO_A_BSRR   (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 16)
#define PTR_STM32_GPIO_B_BSRR   (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 16)
#define PTR_STM32_GPIO_C_BSRR   (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 16)
#define PTR_STM32_GPIO_D_BSRR   (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 16)
        #define STM32_GPIO_BSRR_BR_MASK                 (0x0ffff << 16)
        #define STM32_GPIO_BSRR_BS_MASK                 (0x0ffff << 0)



/*
 **********************************************************************
 *port bit reset register
 **********************************************************************
 */
#define PTR_STM32_GPIO_A_BRR    (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 20)
#define PTR_STM32_GPIO_B_BRR    (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 20)
#define PTR_STM32_GPIO_C_BRR    (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 20)
#define PTR_STM32_GPIO_D_BRR    (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 20)
        #define STM32_GPIO_BR_MASK                      0x0ffff



/*
 **********************************************************************
 *port configuration lock register
 **********************************************************************
 */
#define PTR_STM32_GPIO_A_LCKR   (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 24)
#define PTR_STM32_GPIO_B_LCKR   (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 24)
#define PTR_STM32_GPIO_C_LCKR   (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 24)
#define PTR_STM32_GPIO_D_LCKR   (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 24)
        #define STM32_GPIO_LCKR_MASK                    0x1ffff
        #define STM32_GPIO_LCKR_LCKK                    0x10000



#endif