/*
**********************************************************************
*name: IE_stm32_core.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_core.c header
**********************************************************************
*/
#ifndef IE_STM32_CORE
#define IE_STM32_CORE
/*
**********************************************************************
*determine the number of interrupt lines supported
**********************************************************************
*/
#define PTR_STM32_NVIC_INTCT (volatile unsigned int *)0xe000e004
#define STM32_NVIC_INTCT_INTLINESNUM_OFFSET 0
#define STM32_NVIC_INTCT_INTLINESNUM_MASK 0x1f
/*
**********************************************************************
*used to enable systick features
**********************************************************************
*/
#define PTR_STM32_NVIC_SYSTCSR (volatile unsigned int *)0xe000e010
#define STM32_NVIC_STCSR_COUNTFLAG (1 << 16)
#define STM32_NVIC_STCSR_CLKSOURCE_CORE (1 << 2)
#define STM32_NVIC_STCSR_TICKINT (1 << 1)
#define STM32_NVIC_STCSR_ENABLE (1 << 0)
/*
**********************************************************************
*used to set systick reload count value
**********************************************************************
*/
#define PTR_STM32_NVIC_SYSTRV (volatile unsigned int *)0xe000e014
#define STM32_NVIC_STRV_RELOAD_OFFSET 0
#define STM32_NVIC_STRV_RELOAD_MASK 0x0ffffff
/*
**********************************************************************
*used to read systick current value register
**********************************************************************
*/
#define PTR_STM32_NVIC_SYSTCV (volatile unsigned int *)0xe000e018
#define STM32_NVIC_STCV_CURRENT_OFFSET 0
#define STM32_NVIC_STCV_CURRENT_MASK 0x0ffffff
/*
**********************************************************************
*interrupt set-enable 0xe000 e100 - 0xe000 e11c. each reg is 32 ints
**********************************************************************
*/
#define PTR_STM32_NVIC_INTSE_BASE (volatile unsigned int *)0xe000e100
#define STM32_NVIC_INTSE_SETENA 1
/*
**********************************************************************
*interrupt clear-enable 0xe000 e180 - 0xe000 e19c. each reg is 32 ints
**********************************************************************
*/
#define PTR_STM32_NVIC_INTCE_BASE (volatile unsigned int *)0xe000e180
#define STM32_NVIC_INTCE_CLRENA 1
/*
**********************************************************************
*interrupt set-pending 0xe000 e200 - 0xe000 e21c. each reg is 32 ints
**********************************************************************
*/
#define PTR_STM32_NVIC_INTSP_BASE (volatile unsigned int *)0xe000e200
#define STM32_NVIC_INTSP_SETPEND 1
/*
**********************************************************************
*interrupt clr-pending 0xe000 e280 - 0xe000 e29c. each reg is 32 ints
**********************************************************************
*/
#define PTR_STM32_NVIC_INTCP_BASE (volatile unsigned int *)0xe000e280
#define STM32_NVIC_INTCP_CLRPEND 1
/*
**********************************************************************
*interrupt set-active-bit 0xe000 e300 - 0xe000 e31c. each reg is 32 ints
**********************************************************************
*/
#define PTR_STM32_NVIC_INTSAB_BASE (volatile unsigned int *)0xe000e300
#define STM32_NVIC_INTSAB_ACTIVE 1
/*
**********************************************************************
*interrupt priority 0xe000 e400 - 0xe000 e41c. 8bit priorities
**********************************************************************
*/
#define PTR_STM32_NVIC_INTP_BASE (volatile unsigned int *)0xe000e400
/*
**********************************************************************
*cpu id base
**********************************************************************
*/
#define PTR_STM32_NVIC_CPUID (volatile unsigned int *)0xe000ed00
#define STM32_NVIC_CPUID_REVISION_OFFSET 0
#define STM32_NVIC_CPUID_REVISION_MASK (0x0f << 0)
#define STM32_NVIC_CPUID_PARTNO_OFFSET 4
#define STM32_NVIC_CPUID_PARTNO_MASK (0x0fff << 4)
#define STM32_NVIC_CPUID_CONSTANT_OFFSET 16
#define STM32_NVIC_CPUID_CONSTANT_MASK (0x0f << 16)
#define STM32_NVIC_CPUID_CONSTANT_VALUE 0x0f
#define STM32_NVIC_CPUID_VARIANT_OFFSET 20
#define STM32_NVIC_CPUID_VARIANT_MASK (0x0f << 20)
#define STM32_NVIC_CPUID_IMPLEMENTER_OFFSET 24
#define STM32_NVIC_CPUID_IMPLEMENTER_MASK (0x0ff<< 24)
/*
**********************************************************************
*interrupt control state
**********************************************************************
*/
#define PTR_STM32_NVIC_INTCS (volatile unsigned int *)0xe000ed04
#define STM32_NVIC_INTCS_VECTACTIVE_OFFSET 0
#define STM32_NVIC_INTCS_VECTACTIVE_MASK (0x0ff << 0)
#define STM32_NVIC_INTCS_VECTPENDING_OFFSET 12
#define STM32_NVIC_INTCS_VECTPENDING_MASK (0x3ff << 12)
#define STM32_NVIC_INTCS_RETTOBASE (1 << 11)
#define STM32_NVIC_INTCS_ISRPENDING (1 << 22)
#define STM32_NVIC_INTCS_ISRPREEMPT (1 << 23)
#define STM32_NVIC_INTCS_PENDSTCLR (1 << 25)
#define STM32_NVIC_INTCS_PENDSTSET (1 << 26)
#define STM32_NVIC_INTCS_PENDSVCLR (1 << 27)
#define STM32_NVIC_INTCS_PENDSVSET (1 << 28)
#define STM32_NVIC_INTCS_NMIPENDSET (1 << 31)
/*
**********************************************************************
*vector table offset register. used to remap ivt table
**********************************************************************
*/
#define PTR_STM32_NVIC_VTOR (volatile unsigned int *)0xe000ed08
#define STM32_NVIC_VTOR_TBLOFF_OFFSET 7
#define STM32_NVIC_VTOR_TBLOFF_MASK 0x0ffffff8
#define STM32_NVIC_VTOR_TBLBASE_ROM (0 << 29)
#define STM32_NVIC_VTOR_TBLBASE_RAM (1 << 29)
/*
**********************************************************************
*application interrupt and reset control register
**********************************************************************
*/
#define PTR_STM32_NVIC_AIRCR (volatile unsigned int *)0xe000ed0c
#define STM32_NVIC_AIRCR_VECTRESET (1 << 0)
#define STM32_NVIC_AIRCR_VECTCLRACTIVE (1 << 1)
#define STM32_NVIC_AIRCR_SYSRESETREQ (1 << 2)
#define STM32_NVIC_AIRCR_PRIGROUP_OFFSET 8
#define STM32_NVIC_AIRCR_PRIGROUP_MASK ((0x7) << 8)
#define STM32_NVIC_AIRCR_ENDIANESS_LITTLE (0 << 15)
#define STM32_NVIC_AIRCR_ENDIANESS_BIG (1 << 15)
#define STM32_NVIC_AIRCR_VECTKEYSTAT_OFFSET 16
#define STM32_NVIC_AIRCR_VECTKEYSTAT_MASK (0x0ffff << 16)
#define STM32_NVIC_AIRCR_VECTKEYSTAT_VALUE 0x0fa05
/*
**********************************************************************
*system control register
**********************************************************************
*/
#define PTR_STM32_NVIC_SCR (volatile unsigned int *)0xe000ed10
#define STM32_NVIC_SCR_SLEEPONEXIT (1 << 1)
#define STM32_NVIC_SCR_SLEEPDEEP (1 << 2)
#define STM32_NVIC_SCR_SEVONPEND (1 << 4)
/*
**********************************************************************
*configuration control register
**********************************************************************
*/
#define PTR_STM32_NVIC_CCR (volatile unsigned int *)0xe000ed14
#define STM32_NVIC_CCR_NONBASETHRENA (1 << 0)
#define STM32_NVIC_CCR_USERSETMPEND (1 << 1)
#define STM32_NVIC_CCR_UNALIGN_TRP (1 << 3)
#define STM32_NVIC_CCR_DIV_0_TRP (1 << 4)
#define STM32_NVIC_CCR_BFHFNMIGN (1 << 8)
#define STM32_NVIC_CCR_STKALIGN_DWORD (0 << 9)
#define STM32_NVIC_CCR_STKALIGN_QWORD (1 << 9)
/*
**********************************************************************
*system handler priority registers 0xe000 ed18,0xe000 ed1c, 0xe000 ed20
**********************************************************************
*/
#define PTR_STM32_NVIC_SHPR_1 (volatile unsigned int *)0xe000ed18
#define PTR_STM32_NVIC_SHPR_2 (volatile unsigned int *)0xe000ed1c
#define PTR_STM32_NVIC_SHPR_3 (volatile unsigned int *)0xe000ed20
/*
**********************************************************************
*system handler control and state register
**********************************************************************
*/
#define PTR_STM32_NVIC_SHCSR (volatile unsigned int *)0xe000ed24
#define STM32_NVIC_SHCS_MEMFAULTACT (1 << 0)
#define STM32_NVIC_SHCS_BUSFAULTACT (1 << 1)
#define STM32_NVIC_SHCS_USGFAULTACT (1 << 3)
#define STM32_NVIC_SHCS_SVCALLACT (1 << 7)
#define STM32_NVIC_SHCS_MONITORACT (1 << 8)
#define STM32_NVIC_SHCS_PENDSVACT (1 << 10)
#define STM32_NVIC_SHCS_SYSTICACT (1 << 11)
#define STM32_NVIC_SHCS_USGFAULTPENDED (1 << 12)
#define STM32_NVIC_SHCS_MEMFAULTPENDED (1 << 13)
#define STM32_NVIC_SHCS_BUSFAULTPENDED (1 << 14)
#define STM32_NVIC_SHCS_SVCALLPENDED (1 << 15)
#define STM32_NVIC_SHCS_MEMFAULTENA (1 << 16)
#define STM32_NVIC_SHCS_BUSFAULTENA (1 << 17)
#define STM32_NVIC_SHCS_USGFAULTENA (1 << 18)
/*
**********************************************************************
*configurable fault status registers
**********************************************************************
*/
#define PTR_STM32_NVIC_CFSR (volatile unsigned int *)0xe000ed28
#define PTR_STM32_NVIC_MMFSR (volatile unsigned int *)0xe000ed28
#define PTR_STM32_NVIC_BFSR (volatile unsigned int *)0xe000ed29
#define PTR_STM32_NVIC_UFSR (volatile unsigned int *)0xe000ed2A
#define STM32_NVIC_CFSR_MMFSR_IACCVIOL (1 << 0)
#define STM32_NVIC_CFSR_MMFSR_DACCVIOL (1 << 1)
#define STM32_NVIC_CFSR_MUNSTKERR (1 << 3)
#define STM32_NVIC_CFSR_MSTKERR (1 << 4)
#define STM32_NVIC_CFSR_MMARVALID (1 << 7)
#define STM32_NVIC_CFSR_IBUSERR (1 << 8)
#define STM32_NVIC_CFSR_PRECISERR (1 << 9)
#define STM32_NVIC_CFSR_IMPRECISERR (1 << 10)
#define STM32_NVIC_CFSR_UNSTKERR (1 << 11)
#define STM32_NVIC_CFSR_STKERR (1 << 12)
#define STM32_NVIC_CFSR_BFARVALID (1 << 15)
#define STM32_NVIC_CFSR_UNDEFINSTR (1 << 24)
#define STM32_NVIC_CFSR_INVSTATE (1 << 25)
#define STM32_NVIC_CFSR_INVPC (1 << 26)
#define STM32_NVIC_CFSR_NOCP (1 << 27)
#define STM32_NVIC_CFSR_UNALIGNED (1 << 30)
#define STM32_NVIC_CFSR_DIVBYZERO (1 << 31)
/*
**********************************************************************
*hard fault status register
**********************************************************************
*/
#define PTR_STM32_NVIC_HFSR (volatile unsigned int *)0xe000ed2c
#define STM32_NVIC_HFSR_VECTTBL (1 << 1)
#define STM32_NVIC_HFSR_FORCED (1 << 30)
#define STM32_NVIC_HFSR_DEBUGEVT (1 << 31)
/*
**********************************************************************
*debug fault status register
**********************************************************************
*/
#define PTR_STM32_NVIC_DFSR (volatile unsigned int *)0xe000ed30
#define STM32_NVIC_DFSR_HALTED (1 << 0)
#define STM32_NVIC_DFSR_BKPT (1 << 1)
#define STM32_NVIC_DFSR_DWTTRAO (1 << 2)
#define STM32_NVIC_DFSR_VCATCH (1 << 3)
#define STM32_NVIC_DFSR_EXTERNAL (1 << 4)
/*
**********************************************************************
*memory manage fault address register
**********************************************************************
*/
#define PTR_STM32_NVIC_MMFAR (volatile unsigned int *)0xe000ed34
/*
**********************************************************************
*bus fault address register
**********************************************************************
*/
#define PTR_STM32_NVIC_BFAR (volatile unsigned int *)0xe000ed38
/*
**********************************************************************
*auxillary fault status register
**********************************************************************
*/
#define PTR_STM32_NVIC_AFSR (volatile unsigned int *)0xe000ed3c
/*
**********************************************************************
*software trigger interrupt register
**********************************************************************
*/
#define PTR_STM32_NVIC_STIR (volatile unsigned int *)0xe000ef00
#define STM32_NVIC_STIR_INTID_OFFSET 0
#define STM32_NVIC_STIR_INTID_MASK (0x1ff << 0)
#endif
Thursday, July 18, 2013
IE_stm32_core.h
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