/*
**********************************************************************
*name: IE_stm32_dma.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_dma header
**********************************************************************
*/
#ifndef IE_STM32_DMA
#define IE_STM32_DMA
#define PTR_STM32_DMA1_BASE 0x40020000
#define PTR_STM32_DMA2_BASE 0x40020400
/*
**********************************************************************
*dma interrupt status register
**********************************************************************
*/
#define PTR_STM32_DMA1_ISR (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 0)
#define PTR_STM32_DMA2_ISR (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 0)
#define STM32_DMA_ISR_TEIF_MASK 0x8888888
#define STM32_DMA_ISR_HTIF_MASK 0x4444444
#define STM32_DMA_ISR_TCIF_MASK 0x2222222
#define STM32_DMA_ISR_GIF_MASK 0x1111111
/*
**********************************************************************
*dma interrupt flag clear register
**********************************************************************
*/
#define PTR_STM32_DMA1_IFCR (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 4)
#define PTR_STM32_DMA2_IFCR (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 4)
#define STM32_DMA_IFCR_CTEIF_MASK 0x8888888
#define STM32_DMA_IFCR_CHTIF_MASK 0x4444444
#define STM32_DMA_IFCR_CTCIF_MASK 0x2222222
#define STM32_DMA_IFCR_CGIF_MASK 0x1111111
/*
**********************************************************************
*dma channel x configuration register
**********************************************************************
*/
#define PTR_STM32_DMA1_CCR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 8)
#define PTR_STM32_DMA1_CCR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 28)
#define PTR_STM32_DMA1_CCR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 48)
#define PTR_STM32_DMA1_CCR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 68)
#define PTR_STM32_DMA1_CCR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 88)
#define PTR_STM32_DMA1_CCR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 108)
#define PTR_STM32_DMA1_CCR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 128)
#define PTR_STM32_DMA2_CCR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 8)
#define PTR_STM32_DMA2_CCR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 28)
#define PTR_STM32_DMA2_CCR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 48)
#define PTR_STM32_DMA2_CCR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 68)
#define PTR_STM32_DMA2_CCR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 88)
#define STM32_DMA_CCR_MEM2MEM_ENABLED (1 << 14)
#define STM32_DMA_CCR_PL_OFFSET 12
#define STM32_DMA_CCR_PL_MASK 0x3
#define STM32_DMA_CCR_PL_LOW (0 << 12)
#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
#define STM32_DMA_CCR_PL_HIGH (2 << 12)
#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
#define STM32_DMA_CCR_MSIZE_OFFSET 10
#define STM32_DMA_CCR_MSIZE_MASK 0x3
#define STM32_DMA_CCR_MSIZE_8 (0 << 10)
#define STM32_DMA_CCR_MSIZE_16 (1 << 10)
#define STM32_DMA_CCR_MSIZE_32 (2 << 10)
#define STM32_DMA_CCR_PSIZE_OFFSET 8
#define STM32_DMA_CCR_PSIZE_MASK 0x3
#define STM32_DMA_CCR_PSIZE_8 (0 << 8)
#define STM32_DMA_CCR_PSIZE_16 (1 << 8)
#define STM32_DMA_CCR_PSIZE_32 (2 << 8)
#define STM32_DMA_CCR_MINC (1 << 7)
#define STM32_DMA_CCR_PINC (1 << 6)
#define STM32_DMA_CCR_CIRC (1 << 5)
#define STM32_DMA_CCR_DIR_FROM_PERIPHERAL (0 << 4)
#define STM32_DMA_CCR_DIR_FROM_MEMORY (1 << 4)
#define STM32_DMA_CCR_TEIE (1 << 3)
#define STM32_DMA_CCR_HTIE (1 << 2)
#define STM32_DMA_CCR_TCIE (1 << 1)
#define STM32_DMA_CCR_EN (1 << 0)
/*
**********************************************************************
*dma channel x number of data register
**********************************************************************
*/
#define PTR_STM32_DMA1_CNDTR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 12)
#define PTR_STM32_DMA1_CNDTR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 32)
#define PTR_STM32_DMA1_CNDTR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 52)
#define PTR_STM32_DMA1_CNDTR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 72)
#define PTR_STM32_DMA1_CNDTR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 92)
#define PTR_STM32_DMA1_CNDTR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 112)
#define PTR_STM32_DMA1_CNDTR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 132)
#define PTR_STM32_DMA2_CNDTR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 12)
#define PTR_STM32_DMA2_CNDTR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 32)
#define PTR_STM32_DMA2_CNDTR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 52)
#define PTR_STM32_DMA2_CNDTR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 72)
#define PTR_STM32_DMA2_CNDTR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 92)
#define STM32_DMA_CNDTR_MASK 0x0ffff
/*
**********************************************************************
*dma channel x peripheral address register
**********************************************************************
*/
#define PTR_STM32_DMA1_CPAR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 16)
#define PTR_STM32_DMA1_CPAR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 36)
#define PTR_STM32_DMA1_CPAR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 56)
#define PTR_STM32_DMA1_CPAR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 76)
#define PTR_STM32_DMA1_CPAR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 96)
#define PTR_STM32_DMA1_CPAR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 116)
#define PTR_STM32_DMA1_CPAR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 136)
#define PTR_STM32_DMA2_CPAR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 16)
#define PTR_STM32_DMA2_CPAR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 36)
#define PTR_STM32_DMA2_CPAR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 56)
#define PTR_STM32_DMA2_CPAR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 76)
#define PTR_STM32_DMA2_CPAR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 96)
/*
**********************************************************************
*dma channel x memory address register
**********************************************************************
*/
#define PTR_STM32_DMA1_CMAR1 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 20)
#define PTR_STM32_DMA1_CMAR2 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 40)
#define PTR_STM32_DMA1_CMAR3 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 60)
#define PTR_STM32_DMA1_CMAR4 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 80)
#define PTR_STM32_DMA1_CMAR5 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 100)
#define PTR_STM32_DMA1_CMAR6 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 120)
#define PTR_STM32_DMA1_CMAR7 (volatile unsigned int *)(PTR_STM32_DMA1_BASE + 140)
#define PTR_STM32_DMA2_CMAR1 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 20)
#define PTR_STM32_DMA2_CMAR2 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 40)
#define PTR_STM32_DMA2_CMAR3 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 60)
#define PTR_STM32_DMA2_CMAR4 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 80)
#define PTR_STM32_DMA2_CMAR5 (volatile unsigned int *)(PTR_STM32_DMA2_BASE + 100)
#endif
Monday, July 29, 2013
IE_stm32_dma.h
Thursday, July 18, 2013
IE_stm32_usb.h
/*
**********************************************************************
*name: IE_stm32_usb.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_usb header
**********************************************************************
*/
#ifndef IE_STM32_USB
#define IE_STM32_USB
#define PTR_STM32_USB_BASE 0x40005c00
#define PTR_STM32_USB_EPRAM 0x40006000
/*
**********************************************************************
*usb base address
**********************************************************************
*/
#define PTR_STM32_USB_BTABLE (volatile unsigned int *)(PTR_STM32_USB_BASE + 80)
/*
**********************************************************************
*usb control register
**********************************************************************
*/
#define PTR_STM32_USB_CNTR (volatile unsigned int *)(PTR_STM32_USB_BASE + 64)
#define STM32_USB_CNTR_CTRM (1 << 15)
#define STM32_USB_CNTR_PMAOVRM (1 << 14)
#define STM32_USB_CNTR_ERRM (1 << 13)
#define STM32_USB_CNTR_WKUPM (1 << 12)
#define STM32_USB_CNTR_SUSPM (1 << 11)
#define STM32_USB_CNTR_RESETM (1 << 10)
#define STM32_USB_CNTR_SOFM (1 << 9)
#define STM32_USB_CNTR_ESOFM (1 << 8)
#define STM32_USB_CNTR_RESUME (1 << 4)
#define STM32_USB_CNTR_FSUSP (1 << 3)
#define STM32_USB_CNTR_LP_MODE (1 << 2)
#define STM32_USB_CNTR_PDWN (1 << 1)
#define STM32_USB_CNTR_FRES (1 << 0)
/*
**********************************************************************
*usb interrupt status register
**********************************************************************
*/
#define PTR_STM32_USB_ISTR (volatile unsigned int *)(PTR_STM32_USB_BASE + 68)
#define STM32_USB_ISTR_CTR (1 << 15)
#define STM32_USB_ISTR_PMAOVR (1 << 14)
#define STM32_USB_ISTR_ERR (1 << 13)
#define STM32_USB_ISTR_WKUP (1 << 12)
#define STM32_USB_ISTR_SUSP (1 << 11)
#define STM32_USB_ISTR_RESET (1 << 10)
#define STM32_USB_ISTR_SOF (1 << 9)
#define STM32_USB_ISTR_ESOF (1 << 8)
#define STM32_USB_ISTR_DIR_MASK (1 << 4)
#define STM32_USB_ISTR_DIR_IN (0 << 4)
#define STM32_USB_ISTR_DIR_OUT (1 << 4)
#define STM32_USB_ISTR_EP_ID_OFFSET 0
#define STM32_USB_ISTR_EP_ID_MASK (0x0f << 0)
/*
**********************************************************************
*usb interrupt status register
**********************************************************************
*/
#define PTR_STM32_USB_FNR (volatile unsigned int *)(PTR_STM32_USB_BASE + 72)
#define STM32_USB_FNR_RXDP (1 << 15)
#define STM32_USB_FNR_RXDM (1 << 14)
#define STM32_USB_FNR_LCK (1 << 13)
#define STM32_USB_FNR_LSOF_OFFSET 11
#define STM32_USB_FNR_LSOF_MASK (0x3 << 11)
#define STM32_USB_FNR_FN_OFFSET 0
#define STM32_USB_FNR_FN_MASK (0x7ff << 0)
/*
**********************************************************************
*usb device address register
**********************************************************************
*/
#define PTR_STM32_USB_DADDR (volatile unsigned int *)(PTR_STM32_USB_BASE + 76)
#define STM32_USB_DADDR_EF (1 << 7)
#define STM32_USB_DADDR_ADD_OFFSET 0
#define STM32_USB_DADDR_ADD_MASK (0x7f << 0)
/*
**********************************************************************
*usb endpoint specific register
**********************************************************************
*/
#define PTR_STM32_USB_EP0R (volatile unsigned int *)(PTR_STM32_USB_BASE + 0)
#define PTR_STM32_USB_EP1R (volatile unsigned int *)(PTR_STM32_USB_BASE + 4)
#define PTR_STM32_USB_EP2R (volatile unsigned int *)(PTR_STM32_USB_BASE + 8)
#define PTR_STM32_USB_EP3R (volatile unsigned int *)(PTR_STM32_USB_BASE + 12)
#define PTR_STM32_USB_EP4R (volatile unsigned int *)(PTR_STM32_USB_BASE + 16)
#define PTR_STM32_USB_EP5R (volatile unsigned int *)(PTR_STM32_USB_BASE + 20)
#define PTR_STM32_USB_EP6R (volatile unsigned int *)(PTR_STM32_USB_BASE + 24)
#define PTR_STM32_USB_EP7R (volatile unsigned int *)(PTR_STM32_USB_BASE + 28)
#define STM32_USB_EPR_CTR_RX (1 << 15)
#define STM32_USB_EPR_DTOG_RX (1 << 14)
#define STM32_USB_EPR_DTOG_RX_OFFSET 14
#define STM32_USB_EPR_STAT_RX_OFFSET 12
#define STM32_USB_EPR_STAT_RX_MASK (0x3 << 12)
#define STM32_USB_EPR_STAT_RX_DISABLE 0
#define STM32_USB_EPR_STAT_RX_STALL 1
#define STM32_USB_EPR_STAT_RX_NAK 2
#define STM32_USB_EPR_STAT_RX_VALID 3
#define STM32_USB_EPR_SETUP (1 << 11)
#define STM32_USB_EPR_EP_TYPE_OFFSET 9
#define STM32_USB_EPR_EP_TYPE_MASK (0x3 << 9)
#define STM32_USB_EPR_EP_TYPE_BULK 0
#define STM32_USB_EPR_EP_TYPE_CONTROL 1
#define STM32_USB_EPR_EP_TYPE_ISO 2
#define STM32_USB_EPR_EP_TYPE_INTERRUPT 3
#define STM32_USB_EPR_EP_KIND (1 << 8)
#define STM32_USB_EPR_CTR_TX (1 << 7)
#define STM32_USB_EPR_DTOG_TX (1 << 6)
#define STM32_USB_EPR_DTOG_TX_OFFSET 6
#define STM32_USB_EPR_STAT_TX_OFFSET 4
#define STM32_USB_EPR_STAT_TX_MASK (0x3 << 4)
#define STM32_USB_EPR_STAT_TX_DISABLE 0
#define STM32_USB_EPR_STAT_TX_STALL 1
#define STM32_USB_EPR_STAT_TX_NAK 2
#define STM32_USB_EPR_STAT_TX_VALID 3
#define STM32_USB_EPR_EA_OFFSET 0
#define STM32_USB_EPR_EA_MASK (0x0f << 0)
/*
**********************************************************************
*usb buffer description table. I can put the buffer description table
*anyway in the 512 memory I choose to put it in the beginning. this
*should be addressed as short (16 bits)
*
*transmission buffer address n
**********************************************************************
*/
#define PTR_STM32_USB_ADDR0_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 0)
#define PTR_STM32_USB_ADDR1_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 8)
#define PTR_STM32_USB_ADDR2_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 16)
#define PTR_STM32_USB_ADDR3_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 24)
#define PTR_STM32_USB_ADDR4_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 32)
#define PTR_STM32_USB_ADDR5_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 40)
#define PTR_STM32_USB_ADDR6_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 48)
#define PTR_STM32_USB_ADDR7_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 56)
#define STM32_USB_ADDR_TX_OFFSET 1
#define STM32_USB_ADDR_TX_MASK (0x7fff << 1)
/*
**********************************************************************
*transmission byte count n
**********************************************************************
*/
#define PTR_STM32_USB_COUNT0_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 2)
#define PTR_STM32_USB_COUNT1_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 10)
#define PTR_STM32_USB_COUNT2_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 18)
#define PTR_STM32_USB_COUNT3_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 26)
#define PTR_STM32_USB_COUNT4_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 34)
#define PTR_STM32_USB_COUNT5_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 42)
#define PTR_STM32_USB_COUNT6_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 50)
#define PTR_STM32_USB_COUNT7_TX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 58)
#define STM32_USB_COUNT_TX_OFFSET 0
#define STM32_USB_COUNT_TX_MASK (0x3ff << 0)
/*
**********************************************************************
*reception buffer address n
**********************************************************************
*/
#define PTR_STM32_USB_ADDR0_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 4)
#define PTR_STM32_USB_ADDR1_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 12)
#define PTR_STM32_USB_ADDR2_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 20)
#define PTR_STM32_USB_ADDR3_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 28)
#define PTR_STM32_USB_ADDR4_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 36)
#define PTR_STM32_USB_ADDR5_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 44)
#define PTR_STM32_USB_ADDR6_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 52)
#define PTR_STM32_USB_ADDR7_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 60)
#define STM32_USB_ADDR_RX_OFFSET 1
#define STM32_USB_ADDR_RX_MASK (0x7fff << 1)
/*
**********************************************************************
*reception byte count n
**********************************************************************
*/
#define PTR_STM32_USB_COUNT0_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 6)
#define PTR_STM32_USB_COUNT1_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 14)
#define PTR_STM32_USB_COUNT2_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 22)
#define PTR_STM32_USB_COUNT3_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 30)
#define PTR_STM32_USB_COUNT4_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 38)
#define PTR_STM32_USB_COUNT5_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 46)
#define PTR_STM32_USB_COUNT6_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 54)
#define PTR_STM32_USB_COUNT7_RX (volatile unsigned short *)(PTR_STM32_USB_EPRAM + 62)
#define STM32_USB_COUNT_RX_BL_SIZE_MASK (1 << 15)
#define STM32_USB_COUNT_RX_BL_SIZE_2BYTE (0 << 15)
#define STM32_USB_COUNT_RX_BL_SIZE_32BYTE (1 << 15)
#define STM32_USB_COUNT_RX_NUM_BLOCK_OFFSET 10
#define STM32_USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << 10)
#define STM32_USB_COUNT_RX_OFFSET 0
#define STM32_USB_COUNT_RX_MASK (0x3ff << 0)
/*
**********************************************************************
*module routines
**********************************************************************
*/
void stm32_usb_init(void);
void stm32_usb_pre_reset_setup(unsigned int wdEndPNum,\
unsigned int wdEndPType,\
unsigned int wdEndPSize);
void stm32_usb_post_reset_setup(unsigned int wdEndPNum,\
unsigned int wdEndPType,\
unsigned int wdEndPSize);
int stm32_usb_endp_send_packet(unsigned int wdEndPNum,\
unsigned char *ptrBuffer,\
unsigned int wdEndPSize,\
unsigned int wdBytelen);
int stm32_usb_build_endp_descriptors(unsigned int wdEndPNum,\
unsigned int wdEndPType,\
unsigned int wdEndPSize,\
unsigned int *ptrDescAddr,\
unsigned int wdLclPktAddr);
int stm32_usb_endp_get_packet(unsigned int wdEndPNum,\
unsigned char *ptrBuffer,\
unsigned int wdBytelen);
void stm32_usb_connect_pullup(unsigned int wdPin);
void stm32_usb_disconnect_pullup(unsigned int wdPin);
#endif
IE_stm32_uart.h
/*
**********************************************************************
*name: IE_stm32_uart.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_uart header
**********************************************************************
*/
#ifndef IE_STM32_UART
#define IE_STM32_UART
#define PTR_STM32_UART1_BASE 0x40013800
#define PTR_STM32_UART2_BASE 0x40004400
#define PTR_STM32_UART3_BASE 0x40004800
#define PTR_STM32_UART4_BASE 0x40004c00
/*
**********************************************************************
*uart status register
**********************************************************************
*/
#define PTR_STM32_UART1_SR (volatile unsigned int *)(PTR_STM32_UART1_BASE + 0)
#define PTR_STM32_UART2_SR (volatile unsigned int *)(PTR_STM32_UART2_BASE + 0)
#define PTR_STM32_UART3_SR (volatile unsigned int *)(PTR_STM32_UART3_BASE + 0)
#define PTR_STM32_UART4_SR (volatile unsigned int *)(PTR_STM32_UART4_BASE + 0)
#define STM32_UART_SR_CTS (1 << 9)
#define STM32_UART_SR_LBD (1 << 8)
#define STM32_UART_SR_TXE (1 << 7)
#define STM32_UART_SR_TC (1 << 6)
#define STM32_UART_SR_RXNE (1 << 5)
#define STM32_UART_SR_IDLE (1 << 4)
#define STM32_UART_SR_ORE (1 << 3)
#define STM32_UART_SR_NE (1 << 2)
#define STM32_UART_SR_FE (1 << 1)
#define STM32_UART_SR_PE (1 << 0)
/*
**********************************************************************
*uart data register
**********************************************************************
*/
#define PTR_STM32_UART1_DR (volatile unsigned int *)(PTR_STM32_UART1_BASE + 4)
#define PTR_STM32_UART2_DR (volatile unsigned int *)(PTR_STM32_UART2_BASE + 4)
#define PTR_STM32_UART3_DR (volatile unsigned int *)(PTR_STM32_UART3_BASE + 4)
#define PTR_STM32_UART4_DR (volatile unsigned int *)(PTR_STM32_UART4_BASE + 4)
#define STM32_UART_DR_MASK (0x1ff << 0)
/*
**********************************************************************
*uart baud rate register
*using a 72Mhz clock and a baudrate of 115200 means this register
*should be set to 0x291
**********************************************************************
*/
#define PTR_STM32_UART1_BRR (volatile unsigned int *)(PTR_STM32_UART1_BASE + 8)
#define PTR_STM32_UART2_BRR (volatile unsigned int *)(PTR_STM32_UART2_BASE + 8)
#define PTR_STM32_UART3_BRR (volatile unsigned int *)(PTR_STM32_UART3_BASE + 8)
#define PTR_STM32_UART4_BRR (volatile unsigned int *)(PTR_STM32_UART4_BASE + 8)
#define STM32_UART_BRR_DIV_MANTISSA_OFFSET 4
#define STM32_UART_BRR_DIV_MANTISSA_MASK (0x0fff << 4)
#define STM32_UART_BRR_DIV_FRACTION_OFFSET 0
#define STM32_UART_BRR_DIV_FRACTION_MASK (0x0f << 0)
/*
**********************************************************************
*uart control register1
**********************************************************************
*/
#define PTR_STM32_UART1_CR1 (volatile unsigned int *)(PTR_STM32_UART1_BASE + 12)
#define PTR_STM32_UART2_CR1 (volatile unsigned int *)(PTR_STM32_UART2_BASE + 12)
#define PTR_STM32_UART3_CR1 (volatile unsigned int *)(PTR_STM32_UART3_BASE + 12)
#define PTR_STM32_UART4_CR1 (volatile unsigned int *)(PTR_STM32_UART4_BASE + 12)
#define STM32_UART_CR1_UE (1 << 13)
#define STM32_UART_CR1_M (1 << 12)
#define STM32_UART_CR1_WAKE (1 << 11)
#define STM32_UART_CR1_PCE (1 << 10)
#define STM32_UART_CR1_PS (1 << 9)
#define STM32_UART_CR1_PEIE (1 << 8)
#define STM32_UART_CR1_TXEIE (1 << 7)
#define STM32_UART_CR1_TCIE (1 << 6)
#define STM32_UART_CR1_RXNEIE (1 << 5)
#define STM32_UART_CR1_IDLEIE (1 << 4)
#define STM32_UART_CR1_TE (1 << 3)
#define STM32_UART_CR1_RE (1 << 2)
#define STM32_UART_CR1_RWU (1 << 1)
#define STM32_UART_CR1_SBK (1 << 0)
/*
**********************************************************************
*uart control register2
**********************************************************************
*/
#define PTR_STM32_UART1_CR2 (volatile unsigned int *)(PTR_STM32_UART1_BASE + 16)
#define PTR_STM32_UART2_CR2 (volatile unsigned int *)(PTR_STM32_UART2_BASE + 16)
#define PTR_STM32_UART3_CR2 (volatile unsigned int *)(PTR_STM32_UART3_BASE + 16)
#define PTR_STM32_UART4_CR2 (volatile unsigned int *)(PTR_STM32_UART4_BASE + 16)
#define STM32_UART_CR2_LINEN (1 << 14)
#define STM32_UART_CR2_STOP_OFFSET 12
#define STM32_UART_CR2_STOP_MASK (0x3 << 12)
#define STM32_UART_CR2_STOP_1_BIT 0
#define STM32_UART_CR2_STOP_0P5_BIT 1
#define STM32_UART_CR2_STOP_2_BIT 2
#define STM32_UART_CR2_STOP_1P5_BIT 3
#define STM32_UART_CR2_CLKEN (1 << 11)
#define STM32_UART_CR2_CPOL (1 << 10)
#define STM32_UART_CR2_CPHA (1 << 9)
#define STM32_UART_CR2_LBCL (1 << 8)
#define STM32_UART_CR2_LBDIE (1 << 6)
#define STM32_UART_CR2_LBDL (1 << 5)
#define STM32_UART_CR2_ADD_OFFSET 0
#define STM32_UART_CR2_ADD_MASK (0x0f << 0)
/*
**********************************************************************
*uart control register3
**********************************************************************
*/
#define PTR_STM32_UART1_CR3 (volatile unsigned int *)(PTR_STM32_UART1_BASE + 20)
#define PTR_STM32_UART2_CR3 (volatile unsigned int *)(PTR_STM32_UART2_BASE + 20)
#define PTR_STM32_UART3_CR3 (volatile unsigned int *)(PTR_STM32_UART3_BASE + 20)
#define PTR_STM32_UART4_CR3 (volatile unsigned int *)(PTR_STM32_UART4_BASE + 20)
#define STM32_UART_CR3_CTSIE (1 << 10)
#define STM32_UART_CR3_CTSE (1 << 9)
#define STM32_UART_CR3_RTSE (1 << 8)
#define STM32_UART_CR3_DMAT (1 << 7)
#define STM32_UART_CR3_DMAR (1 << 6)
#define STM32_UART_CR3_SCEN (1 << 5)
#define STM32_UART_CR3_NACK (1 << 4)
#define STM32_UART_CR3_HDSEL (1 << 3)
#define STM32_UART_CR3_IRLP (1 << 2)
#define STM32_UART_CR3_IREN (1 << 1)
#define STM32_UART_CR3_EIE (1 << 0)
/*
**********************************************************************
*uart control register3
**********************************************************************
*/
#define PTR_STM32_UART1_GTPR (volatile unsigned int *)(PTR_STM32_UART1_BASE + 24)
#define PTR_STM32_UART2_GTPR (volatile unsigned int *)(PTR_STM32_UART2_BASE + 24)
#define PTR_STM32_UART3_GTPR (volatile unsigned int *)(PTR_STM32_UART3_BASE + 24)
#define PTR_STM32_UART4_GTPR (volatile unsigned int *)(PTR_STM32_UART4_BASE + 24)
#define STM32_UART_CR3_GT_OFFSET 8
#define STM32_UART_CR3_GT_MASK (0x0ff << 8)
#define STM32_UART_CR3_PSC_OFFSET 0
#define STM32_UART_CR3_PSC_MASK (0x0ff << 0)
#endif
IE_stm32_rstcc.h
/*
**********************************************************************
*name: IE_stm32_rstcc.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_rstcc header
**********************************************************************
*/
#ifndef IE_STM32_RSTCC
#define IE_STM32_RSTCC
#define PTR_STM32_RCC_BASE 0x40021000
/*
**********************************************************************
*clock control register
**********************************************************************
*/
#define PTR_STM32_RCC_CR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 0)
#define STM32_RCC_CR_PLLRDY (1 << 25)
#define STM32_RCC_CR_PLLON (1 << 24)
#define STM32_RCC_CR_CSSON (1 << 19)
#define STM32_RCC_CR_HSEBYP (1 << 18)
#define STM32_RCC_CR_HSERDY (1 << 17)
#define STM32_RCC_CR_HSEON (1 << 16)
#define STM32_RCC_CR_HSICAL_OFFSET 8
#define STM32_RCC_CR_HSICAL_MASK (0x0ff << 8)
#define STM32_RCC_CR_HSITRIM_OFFSET 3
#define STM32_RCC_CR_HSITRIM_MASK (0x1f << 3)
#define STM32_RCC_CR_HSIRDY (1 << 1)
#define STM32_RCC_CR_HSION (1 << 0)
/*
**********************************************************************
*clock configuration register
**********************************************************************
*/
#define PTR_STM32_RCC_CFGR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 4)
#define STM32_RCC_CFGR_MCO_OFFSET 24
#define STM32_RCC_CFGR_MCO_MASK (0x7 << 24)
#define STM32_RCC_CFGR_MCO_NOCLK (0 << 24)
#define STM32_RCC_CFGR_MCO_SYSCLK (4 << 24)
#define STM32_RCC_CFGR_MCO_HSI (5 << 24)
#define STM32_RCC_CFGR_MCO_HSE (6 << 24)
#define STM32_RCC_CFGR_MCO_PLL (7 << 24)
#define STM32_RCC_CFGR_USBPRE (1 << 22)
#define STM32_RCC_CFGR_PLLMUL_OFFSET 18
#define STM32_RCC_CFGR_PLLMUL_MASK (0x0f << 18)
#define STM32_RCC_CFGR_PLLMUL_ADJUSTMENT 2
#define STM32_RCC_CFGR_PLLXTPRE (1 << 17)
#define STM32_RCC_CFGR_PLLSRC (1 << 16)
#define STM32_RCC_CFGR_ADCPRE_OFFSET 14
#define STM32_RCC_CFGR_ADCPRE_MASK (0x3 << 14)
#define STM32_RCC_CFGR_ADCPRE_BY_2 0
#define STM32_RCC_CFGR_ADCPRE_BY_4 1
#define STM32_RCC_CFGR_ADCPRE_BY_6 2
#define STM32_RCC_CFGR_ADCPRE_BY_8 3
#define STM32_RCC_CFGR_PPRE2_OFFSET 11
#define STM32_RCC_CFGR_PPRE2_MASK (0x7 << 11)
#define STM32_RCC_CFGR_PPRE2_NODIV 0
#define STM32_RCC_CFGR_PPRE2_BY_2 4
#define STM32_RCC_CFGR_PPRE2_BY_4 5
#define STM32_RCC_CFGR_PPRE2_BY_8 6
#define STM32_RCC_CFGR_PPRE2_BY_16 7
#define STM32_RCC_CFGR_PPRE1_OFFSET 8
#define STM32_RCC_CFGR_PPRE1_MASK (0x7 << 8)
#define STM32_RCC_CFGR_PPRE1_NODIV 0
#define STM32_RCC_CFGR_PPRE1_2 4
#define STM32_RCC_CFGR_PPRE1_4 5
#define STM32_RCC_CFGR_PPRE1_8 6
#define STM32_RCC_CFGR_PPRE1_16 7
#define STM32_RCC_CFGR_HPRE_OFFSET 4
#define STM32_RCC_CFGR_HPRE_MASK (0x0f << 4)
#define STM32_RCC_CFGR_HPRE_NODIV 0
#define STM32_RCC_CFGR_HPRE_BY_2 9
#define STM32_RCC_CFGR_HPRE_BY_4 10
#define STM32_RCC_CFGR_HPRE_BY_16 11
#define STM32_RCC_CFGR_HPRE_BY_64 12
#define STM32_RCC_CFGR_HPRE_BY_128 13
#define STM32_RCC_CFGR_HPRE_BY_256 14
#define STM32_RCC_CFGR_HPRE_BY_512 15
#define STM32_RCC_CFGR_SWS_OFFSET 2
#define STM32_RCC_CFGR_SWS_MASK (0x3 << 2)
#define STM32_RCC_CFGR_SWS_HSI 0
#define STM32_RCC_CFGR_SWS_HSE 1
#define STM32_RCC_CFGR_SWS_PLL 2
#define STM32_RCC_CFGR_SW_OFFSET 0
#define STM32_RCC_CFGR_SW_MASK (0x3 << 0)
#define STM32_RCC_CFGR_SW_HSI 0
#define STM32_RCC_CFGR_SW_HSE 1
#define STM32_RCC_CFGR_SW_PLL 2
/*
**********************************************************************
*clock interrupt register
**********************************************************************
*/
#define PTR_STM32_RCC_CIR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 8)
#define STM32_RCC_CIR_CSSC (1 << 24)
#define STM32_RCC_CIR_PLLRDYC (1 << 20)
#define STM32_RCC_CIR_HSERDYC (1 << 19)
#define STM32_RCC_CIR_HSIRDYC (1 << 18)
#define STM32_RCC_CIR_LSERDYC (1 << 17)
#define STM32_RCC_CIR_LSIRDYC (1 << 16)
#define STM32_RCC_CIR_PLLRDYIE (1 << 12)
#define STM32_RCC_CIR_HSERDYIE (1 << 11)
#define STM32_RCC_CIR_HSIRDYIE (1 << 10)
#define STM32_RCC_CIR_LSERDYIE (1 << 9)
#define STM32_RCC_CIR_LSIRDYIE (1 << 8)
#define STM32_RCC_CIR_CSSF (1 << 7)
#define STM32_RCC_CIR_PLLRDYF (1 << 4)
#define STM32_RCC_CIR_HSERDYF (1 << 3)
#define STM32_RCC_CIR_HSIRDYF (1 << 2)
#define STM32_RCC_CIR_LSERDYF (1 << 1)
#define STM32_RCC_CIR_LSIRDYF (1 << 0)
/*
**********************************************************************
*apb2 peripheral reset register
**********************************************************************
*/
#define PTR_STM32_RCC_APB2RSTR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 12)
#define STM32_RCC_APB2RSTR_TIM11RST (1 << 21)
#define STM32_RCC_APB2RSTR_TIM10RST (1 << 20)
#define STM32_RCC_APB2RSTR_TIM9RST (1 << 19)
#define STM32_RCC_APB2RSTR_ADC3RST (1 << 15)
#define STM32_RCC_APB2RSTR_UART1RST (1 << 14)
#define STM32_RCC_APB2RSTR_TIM8RST (1 << 13)
#define STM32_RCC_APB2RSTR_SPI1RST (1 << 12)
#define STM32_RCC_APB2RSTR_TIM1RST (1 << 11)
#define STM32_RCC_APB2RSTR_ADC2RST (1 << 10)
#define STM32_RCC_APB2RSTR_ADC1RST (1 << 9)
#define STM32_RCC_APB2RSTR_IOPGRST (1 << 8)
#define STM32_RCC_APB2RSTR_IOPFRST (1 << 7)
#define STM32_RCC_APB2RSTR_IOPERST (1 << 6)
#define STM32_RCC_APB2RSTR_IOPDRST (1 << 5)
#define STM32_RCC_APB2RSTR_IOPCRST (1 << 4)
#define STM32_RCC_APB2RSTR_IOPBRST (1 << 3)
#define STM32_RCC_APB2RSTR_IOPARST (1 << 2)
#define STM32_RCC_APB2RSTR_AFIORST (1 << 0)
/*
**********************************************************************
*apb1 peripheral reset register
**********************************************************************
*/
#define PTR_STM32_RCC_APB1RSTR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 16)
#define STM32_RCC_APB1RSTR_DACRST (1 << 29)
#define STM32_RCC_APB1RSTR_PWRRST (1 << 28)
#define STM32_RCC_APB1RSTR_BKPRST (1 << 27)
#define STM32_RCC_APB1RSTR_CANRST (1 << 25)
#define STM32_RCC_APB1RSTR_USBRST (1 << 23)
#define STM32_RCC_APB1RSTR_I2C2RST (1 << 22)
#define STM32_RCC_APB1RSTR_I2C1RST (1 << 21)
#define STM32_RCC_APB1RSTR_UART5RST (1 << 20)
#define STM32_RCC_APB1RSTR_UART4RST (1 << 19)
#define STM32_RCC_APB1RSTR_UART3RST (1 << 18)
#define STM32_RCC_APB1RSTR_UART2RST (1 << 17)
#define STM32_RCC_APB1RSTR_SPI3RST (1 << 15)
#define STM32_RCC_APB1RSTR_SPI2RST (1 << 14)
#define STM32_RCC_APB1RSTR_WWDGRST (1 << 11)
#define STM32_RCC_APB1RSTR_TIM14RST (1 << 8)
#define STM32_RCC_APB1RSTR_TIM13RST (1 << 7)
#define STM32_RCC_APB1RSTR_TIM12RST (1 << 6)
#define STM32_RCC_APB1RSTR_TIM7RST (1 << 5)
#define STM32_RCC_APB1RSTR_TIM6RST (1 << 4)
#define STM32_RCC_APB1RSTR_TIM5RST (1 << 3)
#define STM32_RCC_APB1RSTR_TIM4RST (1 << 2)
#define STM32_RCC_APB1RSTR_TIM3RST (1 << 1)
#define STM32_RCC_APB1RSTR_TIM2RST (1 << 0)
/*
**********************************************************************
*ahb peripheral clock enable register
**********************************************************************
*/
#define PTR_STM32_RCC_AHBENR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 20)
#define STM32_RCC_AHBENR_SDIOEN (1 << 10)
#define STM32_RCC_AHBENR_FSMCEN (1 << 8)
#define STM32_RCC_AHBENR_CRCEN (1 << 6)
#define STM32_RCC_AHBENR_FLITFEN (1 << 4)
#define STM32_RCC_AHBENR_SRAMEN (1 << 2)
#define STM32_RCC_AHBENR_DMA2EN (1 << 1)
#define STM32_RCC_AHBENR_DMA1EN (1 << 0)
/*
**********************************************************************
*apb2 peripheral clock enable register
**********************************************************************
*/
#define PTR_STM32_RCC_APB2ENR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 24)
#define STM32_RCC_APB2ENR_TIM11EN (1 << 21)
#define STM32_RCC_APB2ENR_TIM10EN (1 << 20)
#define STM32_RCC_APB2ENR_TIM9EN (1 << 19)
#define STM32_RCC_APB2ENR_ADC3EN (1 << 15)
#define STM32_RCC_APB2ENR_UART1EN (1 << 14)
#define STM32_RCC_APB2ENR_TIM8EN (1 << 13)
#define STM32_RCC_APB2ENR_SPI1EN (1 << 12)
#define STM32_RCC_APB2ENR_TIM1EN (1 << 11)
#define STM32_RCC_APB2ENR_ADC2EN (1 << 10)
#define STM32_RCC_APB2ENR_ADC1EN (1 << 9)
#define STM32_RCC_APB2ENR_IOPGEN (1 << 8)
#define STM32_RCC_APB2ENR_IOPFEN (1 << 7)
#define STM32_RCC_APB2ENR_IOPEEN (1 << 6)
#define STM32_RCC_APB2ENR_IOPDEN (1 << 5)
#define STM32_RCC_APB2ENR_IOPCEN (1 << 4)
#define STM32_RCC_APB2ENR_IOPBEN (1 << 3)
#define STM32_RCC_APB2ENR_IOPAEN (1 << 2)
#define STM32_RCC_APB2ENR_AFIOEN (1 << 0)
/*
**********************************************************************
*apb1 peripheral clock enable register
**********************************************************************
*/
#define PTR_STM32_RCC_APB1ENR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 28)
#define STM32_RCC_APB1ENR_DACEN (1 << 29)
#define STM32_RCC_APB1ENR_PWREN (1 << 28)
#define STM32_RCC_APB1ENR_BKPEN (1 << 27)
#define STM32_RCC_APB1ENR_CANEN (1 << 25)
#define STM32_RCC_APB1ENR_USBEN (1 << 23)
#define STM32_RCC_APB1ENR_I2C2EN (1 << 22)
#define STM32_RCC_APB1ENR_I2C1EN (1 << 21)
#define STM32_RCC_APB1ENR_UART5EN (1 << 20)
#define STM32_RCC_APB1ENR_UART4EN (1 << 19)
#define STM32_RCC_APB1ENR_UART3EN (1 << 18)
#define STM32_RCC_APB1ENR_UART2EN (1 << 17)
#define STM32_RCC_APB1ENR_SPI3EN (1 << 15)
#define STM32_RCC_APB1ENR_SPI2EN (1 << 14)
#define STM32_RCC_APB1ENR_WWDGEN (1 << 11)
#define STM32_RCC_APB1ENR_TIM14EN (1 << 8)
#define STM32_RCC_APB1ENR_TIM13EN (1 << 7)
#define STM32_RCC_APB1ENR_TIM12EN (1 << 6)
#define STM32_RCC_APB1ENR_TIM7EN (1 << 5)
#define STM32_RCC_APB1ENR_TIM6EN (1 << 4)
#define STM32_RCC_APB1ENR_TIM5EN (1 << 3)
#define STM32_RCC_APB1ENR_TIM4EN (1 << 2)
#define STM32_RCC_APB1ENR_TIM3EN (1 << 1)
#define STM32_RCC_APB1ENR_TIM2EN (1 << 0)
/*
**********************************************************************
*backup domain control register
**********************************************************************
*/
#define PTR_STM32_RCC_BDCR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 32)
#define STM32_RCC_BDCR_BDRST (1 << 16)
#define STM32_RCC_BDCR_RTCEN (1 << 15)
#define STM32_RCC_BDCR_RTCSEL_OFFSET 8
#define STM32_RCC_BDCR_RTCSEL_MASK (0x3 << 8)
#define STM32_RCC_BDCR_RTCSEL_NOCLK 0
#define STM32_RCC_BDCR_RTCSEL_LSE 1
#define STM32_RCC_BDCR_RTCSEL_HSE 3
#define STM32_RCC_BDCR_LSEBYP (1 << 2)
#define STM32_RCC_BDCR_LSERDY (1 << 1)
#define STM32_RCC_BDCR_LSEON (1 << 0)
/*
**********************************************************************
*control/status register
**********************************************************************
*/
#define PTR_STM32_RCC_CSR (volatile unsigned int *)(PTR_STM32_RCC_BASE + 36)
#define STM32_RCC_CSR_LPWRRSTF (1 << 31)
#define STM32_RCC_CSR_WWDGRSTF (1 << 30)
#define STM32_RCC_CSR_IWDGRSTF (1 << 29)
#define STM32_RCC_CSR_SETRSTF (1 << 28)
#define STM32_RCC_CSR_PORRSTF (1 << 27)
#define STM32_RCC_CSR_PINRSTF (1 << 26)
#define STM32_RCC_CSR_RMVF (1 << 24)
#define STM32_RCC_CSR_LSIRDY (1 << 1)
#define STM32_RCC_CSR_LSION (1 << 0)
#endif
IE_stm32_gpio.h
/*
**********************************************************************
*name: IE_stm32_gpio.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_gpio header
**********************************************************************
*/
#ifndef IE_STM32_GPIO
#define IE_STM32_GPIO
#define PTR_STM32_GPIO_A_BASE 0x40010800
#define PTR_STM32_GPIO_B_BASE 0x40010c00
#define PTR_STM32_GPIO_C_BASE 0x40011000
#define PTR_STM32_GPIO_D_BASE 0x40011400
/*
**********************************************************************
*port configuration #defines
**********************************************************************
*/
#define STM32_GPIO_CNF0_OFFSET 2
#define STM32_GPIO_CNF_MASK 3
#define STM32_GPIO_CNF_IN_ANALOG 0
#define STM32_GPIO_CNF_IN_FLOATING 1
#define STM32_GPIO_CNF_IN_PULL_UP_DOWN 2
#define STM32_GPIO_CNF_OUT_GEN_PUSH_PULL 0
#define STM32_GPIO_CNF_OUT_GEN_OPEN_DRAIN 1
#define STM32_GPIO_CNF_OUT_ALT_PUSH_PULL 2
#define STM32_GPIO_CNF_OUT_ALT_OPEN_DRAIN 3
#define STM32_GPIO_MODE1_OFFSET 4
#define STM32_GPIO_MODE_INPUT_MODE 0
#define STM32_GPIO_MODE_OUTPUT_10MHZ 1
#define STM32_GPIO_MODE_OUTPUT_2MHZ 2
#define STM32_GPIO_MODE_OUTPUT_50MHZ 3
/*
**********************************************************************
*port configuration register low
**********************************************************************
*/
#define PTR_STM32_GPIO_A_CRL (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 0)
#define PTR_STM32_GPIO_B_CRL (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 0)
#define PTR_STM32_GPIO_C_CRL (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 0)
#define PTR_STM32_GPIO_D_CRL (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 0)
/*
**********************************************************************
*port configuration register high
**********************************************************************
*/
#define PTR_STM32_GPIO_A_CRH (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 4)
#define PTR_STM32_GPIO_B_CRH (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 4)
#define PTR_STM32_GPIO_C_CRH (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 4)
#define PTR_STM32_GPIO_D_CRH (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 4)
/*
**********************************************************************
*port input data register
**********************************************************************
*/
#define PTR_STM32_GPIO_A_IDR (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 8)
#define PTR_STM32_GPIO_B_IDR (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 8)
#define PTR_STM32_GPIO_C_IDR (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 8)
#define PTR_STM32_GPIO_D_IDR (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 8)
#define STM32_GPIO_IDR_MASK 0x0ffff
/*
**********************************************************************
*port output data register
**********************************************************************
*/
#define PTR_STM32_GPIO_A_ODR (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 12)
#define PTR_STM32_GPIO_B_ODR (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 12)
#define PTR_STM32_GPIO_C_ODR (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 12)
#define PTR_STM32_GPIO_D_ODR (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 12)
#define STM32_GPIO_ODR_MASK 0x0ffff
/*
**********************************************************************
*port bit set/reset register
**********************************************************************
*/
#define PTR_STM32_GPIO_A_BSRR (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 16)
#define PTR_STM32_GPIO_B_BSRR (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 16)
#define PTR_STM32_GPIO_C_BSRR (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 16)
#define PTR_STM32_GPIO_D_BSRR (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 16)
#define STM32_GPIO_BSRR_BR_MASK (0x0ffff << 16)
#define STM32_GPIO_BSRR_BS_MASK (0x0ffff << 0)
/*
**********************************************************************
*port bit reset register
**********************************************************************
*/
#define PTR_STM32_GPIO_A_BRR (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 20)
#define PTR_STM32_GPIO_B_BRR (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 20)
#define PTR_STM32_GPIO_C_BRR (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 20)
#define PTR_STM32_GPIO_D_BRR (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 20)
#define STM32_GPIO_BR_MASK 0x0ffff
/*
**********************************************************************
*port configuration lock register
**********************************************************************
*/
#define PTR_STM32_GPIO_A_LCKR (volatile unsigned int *)(PTR_STM32_GPIO_A_BASE + 24)
#define PTR_STM32_GPIO_B_LCKR (volatile unsigned int *)(PTR_STM32_GPIO_B_BASE + 24)
#define PTR_STM32_GPIO_C_LCKR (volatile unsigned int *)(PTR_STM32_GPIO_C_BASE + 24)
#define PTR_STM32_GPIO_D_LCKR (volatile unsigned int *)(PTR_STM32_GPIO_D_BASE + 24)
#define STM32_GPIO_LCKR_MASK 0x1ffff
#define STM32_GPIO_LCKR_LCKK 0x10000
#endif
IE_stm32_core.h
/*
**********************************************************************
*name: IE_stm32_core.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32_core.c header
**********************************************************************
*/
#ifndef IE_STM32_CORE
#define IE_STM32_CORE
/*
**********************************************************************
*determine the number of interrupt lines supported
**********************************************************************
*/
#define PTR_STM32_NVIC_INTCT (volatile unsigned int *)0xe000e004
#define STM32_NVIC_INTCT_INTLINESNUM_OFFSET 0
#define STM32_NVIC_INTCT_INTLINESNUM_MASK 0x1f
/*
**********************************************************************
*used to enable systick features
**********************************************************************
*/
#define PTR_STM32_NVIC_SYSTCSR (volatile unsigned int *)0xe000e010
#define STM32_NVIC_STCSR_COUNTFLAG (1 << 16)
#define STM32_NVIC_STCSR_CLKSOURCE_CORE (1 << 2)
#define STM32_NVIC_STCSR_TICKINT (1 << 1)
#define STM32_NVIC_STCSR_ENABLE (1 << 0)
/*
**********************************************************************
*used to set systick reload count value
**********************************************************************
*/
#define PTR_STM32_NVIC_SYSTRV (volatile unsigned int *)0xe000e014
#define STM32_NVIC_STRV_RELOAD_OFFSET 0
#define STM32_NVIC_STRV_RELOAD_MASK 0x0ffffff
/*
**********************************************************************
*used to read systick current value register
**********************************************************************
*/
#define PTR_STM32_NVIC_SYSTCV (volatile unsigned int *)0xe000e018
#define STM32_NVIC_STCV_CURRENT_OFFSET 0
#define STM32_NVIC_STCV_CURRENT_MASK 0x0ffffff
/*
**********************************************************************
*interrupt set-enable 0xe000 e100 - 0xe000 e11c. each reg is 32 ints
**********************************************************************
*/
#define PTR_STM32_NVIC_INTSE_BASE (volatile unsigned int *)0xe000e100
#define STM32_NVIC_INTSE_SETENA 1
/*
**********************************************************************
*interrupt clear-enable 0xe000 e180 - 0xe000 e19c. each reg is 32 ints
**********************************************************************
*/
#define PTR_STM32_NVIC_INTCE_BASE (volatile unsigned int *)0xe000e180
#define STM32_NVIC_INTCE_CLRENA 1
/*
**********************************************************************
*interrupt set-pending 0xe000 e200 - 0xe000 e21c. each reg is 32 ints
**********************************************************************
*/
#define PTR_STM32_NVIC_INTSP_BASE (volatile unsigned int *)0xe000e200
#define STM32_NVIC_INTSP_SETPEND 1
/*
**********************************************************************
*interrupt clr-pending 0xe000 e280 - 0xe000 e29c. each reg is 32 ints
**********************************************************************
*/
#define PTR_STM32_NVIC_INTCP_BASE (volatile unsigned int *)0xe000e280
#define STM32_NVIC_INTCP_CLRPEND 1
/*
**********************************************************************
*interrupt set-active-bit 0xe000 e300 - 0xe000 e31c. each reg is 32 ints
**********************************************************************
*/
#define PTR_STM32_NVIC_INTSAB_BASE (volatile unsigned int *)0xe000e300
#define STM32_NVIC_INTSAB_ACTIVE 1
/*
**********************************************************************
*interrupt priority 0xe000 e400 - 0xe000 e41c. 8bit priorities
**********************************************************************
*/
#define PTR_STM32_NVIC_INTP_BASE (volatile unsigned int *)0xe000e400
/*
**********************************************************************
*cpu id base
**********************************************************************
*/
#define PTR_STM32_NVIC_CPUID (volatile unsigned int *)0xe000ed00
#define STM32_NVIC_CPUID_REVISION_OFFSET 0
#define STM32_NVIC_CPUID_REVISION_MASK (0x0f << 0)
#define STM32_NVIC_CPUID_PARTNO_OFFSET 4
#define STM32_NVIC_CPUID_PARTNO_MASK (0x0fff << 4)
#define STM32_NVIC_CPUID_CONSTANT_OFFSET 16
#define STM32_NVIC_CPUID_CONSTANT_MASK (0x0f << 16)
#define STM32_NVIC_CPUID_CONSTANT_VALUE 0x0f
#define STM32_NVIC_CPUID_VARIANT_OFFSET 20
#define STM32_NVIC_CPUID_VARIANT_MASK (0x0f << 20)
#define STM32_NVIC_CPUID_IMPLEMENTER_OFFSET 24
#define STM32_NVIC_CPUID_IMPLEMENTER_MASK (0x0ff<< 24)
/*
**********************************************************************
*interrupt control state
**********************************************************************
*/
#define PTR_STM32_NVIC_INTCS (volatile unsigned int *)0xe000ed04
#define STM32_NVIC_INTCS_VECTACTIVE_OFFSET 0
#define STM32_NVIC_INTCS_VECTACTIVE_MASK (0x0ff << 0)
#define STM32_NVIC_INTCS_VECTPENDING_OFFSET 12
#define STM32_NVIC_INTCS_VECTPENDING_MASK (0x3ff << 12)
#define STM32_NVIC_INTCS_RETTOBASE (1 << 11)
#define STM32_NVIC_INTCS_ISRPENDING (1 << 22)
#define STM32_NVIC_INTCS_ISRPREEMPT (1 << 23)
#define STM32_NVIC_INTCS_PENDSTCLR (1 << 25)
#define STM32_NVIC_INTCS_PENDSTSET (1 << 26)
#define STM32_NVIC_INTCS_PENDSVCLR (1 << 27)
#define STM32_NVIC_INTCS_PENDSVSET (1 << 28)
#define STM32_NVIC_INTCS_NMIPENDSET (1 << 31)
/*
**********************************************************************
*vector table offset register. used to remap ivt table
**********************************************************************
*/
#define PTR_STM32_NVIC_VTOR (volatile unsigned int *)0xe000ed08
#define STM32_NVIC_VTOR_TBLOFF_OFFSET 7
#define STM32_NVIC_VTOR_TBLOFF_MASK 0x0ffffff8
#define STM32_NVIC_VTOR_TBLBASE_ROM (0 << 29)
#define STM32_NVIC_VTOR_TBLBASE_RAM (1 << 29)
/*
**********************************************************************
*application interrupt and reset control register
**********************************************************************
*/
#define PTR_STM32_NVIC_AIRCR (volatile unsigned int *)0xe000ed0c
#define STM32_NVIC_AIRCR_VECTRESET (1 << 0)
#define STM32_NVIC_AIRCR_VECTCLRACTIVE (1 << 1)
#define STM32_NVIC_AIRCR_SYSRESETREQ (1 << 2)
#define STM32_NVIC_AIRCR_PRIGROUP_OFFSET 8
#define STM32_NVIC_AIRCR_PRIGROUP_MASK ((0x7) << 8)
#define STM32_NVIC_AIRCR_ENDIANESS_LITTLE (0 << 15)
#define STM32_NVIC_AIRCR_ENDIANESS_BIG (1 << 15)
#define STM32_NVIC_AIRCR_VECTKEYSTAT_OFFSET 16
#define STM32_NVIC_AIRCR_VECTKEYSTAT_MASK (0x0ffff << 16)
#define STM32_NVIC_AIRCR_VECTKEYSTAT_VALUE 0x0fa05
/*
**********************************************************************
*system control register
**********************************************************************
*/
#define PTR_STM32_NVIC_SCR (volatile unsigned int *)0xe000ed10
#define STM32_NVIC_SCR_SLEEPONEXIT (1 << 1)
#define STM32_NVIC_SCR_SLEEPDEEP (1 << 2)
#define STM32_NVIC_SCR_SEVONPEND (1 << 4)
/*
**********************************************************************
*configuration control register
**********************************************************************
*/
#define PTR_STM32_NVIC_CCR (volatile unsigned int *)0xe000ed14
#define STM32_NVIC_CCR_NONBASETHRENA (1 << 0)
#define STM32_NVIC_CCR_USERSETMPEND (1 << 1)
#define STM32_NVIC_CCR_UNALIGN_TRP (1 << 3)
#define STM32_NVIC_CCR_DIV_0_TRP (1 << 4)
#define STM32_NVIC_CCR_BFHFNMIGN (1 << 8)
#define STM32_NVIC_CCR_STKALIGN_DWORD (0 << 9)
#define STM32_NVIC_CCR_STKALIGN_QWORD (1 << 9)
/*
**********************************************************************
*system handler priority registers 0xe000 ed18,0xe000 ed1c, 0xe000 ed20
**********************************************************************
*/
#define PTR_STM32_NVIC_SHPR_1 (volatile unsigned int *)0xe000ed18
#define PTR_STM32_NVIC_SHPR_2 (volatile unsigned int *)0xe000ed1c
#define PTR_STM32_NVIC_SHPR_3 (volatile unsigned int *)0xe000ed20
/*
**********************************************************************
*system handler control and state register
**********************************************************************
*/
#define PTR_STM32_NVIC_SHCSR (volatile unsigned int *)0xe000ed24
#define STM32_NVIC_SHCS_MEMFAULTACT (1 << 0)
#define STM32_NVIC_SHCS_BUSFAULTACT (1 << 1)
#define STM32_NVIC_SHCS_USGFAULTACT (1 << 3)
#define STM32_NVIC_SHCS_SVCALLACT (1 << 7)
#define STM32_NVIC_SHCS_MONITORACT (1 << 8)
#define STM32_NVIC_SHCS_PENDSVACT (1 << 10)
#define STM32_NVIC_SHCS_SYSTICACT (1 << 11)
#define STM32_NVIC_SHCS_USGFAULTPENDED (1 << 12)
#define STM32_NVIC_SHCS_MEMFAULTPENDED (1 << 13)
#define STM32_NVIC_SHCS_BUSFAULTPENDED (1 << 14)
#define STM32_NVIC_SHCS_SVCALLPENDED (1 << 15)
#define STM32_NVIC_SHCS_MEMFAULTENA (1 << 16)
#define STM32_NVIC_SHCS_BUSFAULTENA (1 << 17)
#define STM32_NVIC_SHCS_USGFAULTENA (1 << 18)
/*
**********************************************************************
*configurable fault status registers
**********************************************************************
*/
#define PTR_STM32_NVIC_CFSR (volatile unsigned int *)0xe000ed28
#define PTR_STM32_NVIC_MMFSR (volatile unsigned int *)0xe000ed28
#define PTR_STM32_NVIC_BFSR (volatile unsigned int *)0xe000ed29
#define PTR_STM32_NVIC_UFSR (volatile unsigned int *)0xe000ed2A
#define STM32_NVIC_CFSR_MMFSR_IACCVIOL (1 << 0)
#define STM32_NVIC_CFSR_MMFSR_DACCVIOL (1 << 1)
#define STM32_NVIC_CFSR_MUNSTKERR (1 << 3)
#define STM32_NVIC_CFSR_MSTKERR (1 << 4)
#define STM32_NVIC_CFSR_MMARVALID (1 << 7)
#define STM32_NVIC_CFSR_IBUSERR (1 << 8)
#define STM32_NVIC_CFSR_PRECISERR (1 << 9)
#define STM32_NVIC_CFSR_IMPRECISERR (1 << 10)
#define STM32_NVIC_CFSR_UNSTKERR (1 << 11)
#define STM32_NVIC_CFSR_STKERR (1 << 12)
#define STM32_NVIC_CFSR_BFARVALID (1 << 15)
#define STM32_NVIC_CFSR_UNDEFINSTR (1 << 24)
#define STM32_NVIC_CFSR_INVSTATE (1 << 25)
#define STM32_NVIC_CFSR_INVPC (1 << 26)
#define STM32_NVIC_CFSR_NOCP (1 << 27)
#define STM32_NVIC_CFSR_UNALIGNED (1 << 30)
#define STM32_NVIC_CFSR_DIVBYZERO (1 << 31)
/*
**********************************************************************
*hard fault status register
**********************************************************************
*/
#define PTR_STM32_NVIC_HFSR (volatile unsigned int *)0xe000ed2c
#define STM32_NVIC_HFSR_VECTTBL (1 << 1)
#define STM32_NVIC_HFSR_FORCED (1 << 30)
#define STM32_NVIC_HFSR_DEBUGEVT (1 << 31)
/*
**********************************************************************
*debug fault status register
**********************************************************************
*/
#define PTR_STM32_NVIC_DFSR (volatile unsigned int *)0xe000ed30
#define STM32_NVIC_DFSR_HALTED (1 << 0)
#define STM32_NVIC_DFSR_BKPT (1 << 1)
#define STM32_NVIC_DFSR_DWTTRAO (1 << 2)
#define STM32_NVIC_DFSR_VCATCH (1 << 3)
#define STM32_NVIC_DFSR_EXTERNAL (1 << 4)
/*
**********************************************************************
*memory manage fault address register
**********************************************************************
*/
#define PTR_STM32_NVIC_MMFAR (volatile unsigned int *)0xe000ed34
/*
**********************************************************************
*bus fault address register
**********************************************************************
*/
#define PTR_STM32_NVIC_BFAR (volatile unsigned int *)0xe000ed38
/*
**********************************************************************
*auxillary fault status register
**********************************************************************
*/
#define PTR_STM32_NVIC_AFSR (volatile unsigned int *)0xe000ed3c
/*
**********************************************************************
*software trigger interrupt register
**********************************************************************
*/
#define PTR_STM32_NVIC_STIR (volatile unsigned int *)0xe000ef00
#define STM32_NVIC_STIR_INTID_OFFSET 0
#define STM32_NVIC_STIR_INTID_MASK (0x1ff << 0)
#endif
IE_stm32.h
/*
**********************************************************************
*name: IE_stm32.h
*author: Samuel Igwe
*date: 07/16/2013
*description: Igbo Embedded stm32.c header
**********************************************************************
*/
#ifndef IE_STM32
#define IE_STM32
#include "IE_stm32_core.h"
#include "IE_stm32_uart.h"
#include "IE_stm32_gpio.h"
#include "IE_stm32_dma.h"
#include "IE_stm32_rstcc.h"
#include "IE_stm32_timer.h"
#include "IE_stm32_usb.h"
#include "IE_stm32_usbdev.h"
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
/*
**********************************************************************
*mappings
*PA0 = external wire jumpered to usb d+
*PB9 + PB8 = GPIO (LED)
*PC0 + PC1 = GPIO (SWITCHES)
*PA11+PA12 = USB (alt function)
*PA9 + PA10 = UART (alt function)
**********************************************************************
*/
#define STM32_GPIO_PIN_USB 0
#define STM32_GPIO_PIN_UART_TX 9
#define STM32_GPIO_PIN_UART_RX 10
#define STM32_GPIO_PIN_USB_DPLUS 11
#define STM32_GPIO_PIN_USB_DMINUS 12
#define STM32_GPIO_PIN_LED1 8
#define STM32_GPIO_PIN_LED2 9
#define STM32_GPIO_PIN_SW1 0
#define STM32_GPIO_PIN_SW2 1
/*
**********************************************************************
*init() routines
*nvic_isr() routines
**********************************************************************
*/
void stm32_init(void);
void stm32_nvic_uninstall_isr(unsigned int wdIrqNum);
void stm32_nvic_install_isr(unsigned int wdIrqNum,\
unsigned int wdIsrAddr);
void stm32_uart_puts(unsigned char *ptrString, int wdBytelen);
void stm32_systick_hook_services(void (*ptrFunc)(void));
void stm32_systick_timer_services(void (*ptrFunc)(void));
int stm32_systick_get_mS_tick(void);
int stm32_systick_get_seconds(void);
void stm32_timer_uS_delay(unsigned int wdUs);
#endif
USB development on the stm32
managed to create the #defines for accessing various peripherals on the stm32 board. right now my focus is usb device firmware development so the modules
reset and clock control
gpio
uart
usb
are all I will likely focus on for now.
reset and clock control
gpio
uart
usb
are all I will likely focus on for now.
Lattice ECP2 Advanced Development Board
Final grab on ebay ... price is $500 but it was posted for $150. I managed to get it for $50 (shipping and handling included). Will download lattice diamond later and plus I have the download cable from an earlier XP2 board.
This is for more advanced work like memory controllers, fifos, ethernet and usb implementation, input analog signal and conditioning and serial transport protocols etc. Basically peripherals that dont exist on the Xilinx Spartan3e250
This is for more advanced work like memory controllers, fifos, ethernet and usb implementation, input analog signal and conditioning and serial transport protocols etc. Basically peripherals that dont exist on the Xilinx Spartan3e250
There and back again
So, where was I before abandoning my rombios.livejournal.com blog shortly after the demise of my NXP lpc2378 board?
I was writing usb device firmware and making much success. Had purchased the 12Mbs beagle usb sniffer/protocol analyzer and began digging in ... but I didnt like the design of the lpc2378 usb device interface and the erroneous documentation that came along with it.
Given that the cost of a new lpc2378 would get me 3 or 4 fairly cheap arm cortex-m3 boards (also I have been dying to see what new features were added) I jumped at the opportunity to abandon the arm7tdmi architecture for the cortex-m3.
I have read the Cortex-m3 technical reference manual along with relevant parts (for the peripherals I need on this unit) of the STM32F1xx technical reference manual.
The goal is to get back to where I was before the lpc2378 died. And since I am big on following murphys law I bought a second STM23F1xx board ... from ebay for about $22 (shipping and handling included). This one will be the backup should something happen to the one I am currently using. Basically its an STM32F103rb verses an STM32F103c8
Ill be doing usb device firmware development in parallel with re-learning verilog on the Xilinx Spartan Board xcv250* while reading Michael D. Ciletti' Advanced Digital Design With Verilog HDL
I was writing usb device firmware and making much success. Had purchased the 12Mbs beagle usb sniffer/protocol analyzer and began digging in ... but I didnt like the design of the lpc2378 usb device interface and the erroneous documentation that came along with it.
Given that the cost of a new lpc2378 would get me 3 or 4 fairly cheap arm cortex-m3 boards (also I have been dying to see what new features were added) I jumped at the opportunity to abandon the arm7tdmi architecture for the cortex-m3.
I have read the Cortex-m3 technical reference manual along with relevant parts (for the peripherals I need on this unit) of the STM32F1xx technical reference manual.
The goal is to get back to where I was before the lpc2378 died. And since I am big on following murphys law I bought a second STM23F1xx board ... from ebay for about $22 (shipping and handling included). This one will be the backup should something happen to the one I am currently using. Basically its an STM32F103rb verses an STM32F103c8
Ill be doing usb device firmware development in parallel with re-learning verilog on the Xilinx Spartan Board xcv250* while reading Michael D. Ciletti' Advanced Digital Design With Verilog HDL
Wednesday, July 17, 2013
ARM Cortex-M3 STM32F103RBT6 Mini Development Board
My NXP/Philips lpc2378 died so I decided now would be a good opportunity to transition from the ARM7TDMI to the Cortex-M3.
Nice investment - $17.20 (total shipping included) from Ebay. Pictures and specs below:
1> Main Chip: STM32F103RBT6
2> Onboard Standard JTAG interface and reset button
3> 2 Onboard crystals, 32.768KHZ and 8MHZ
4> Onboard DC Regulator AMS1117-3.3: 5V input to 3.3V
5> One RS232 serial port, UART1 and UART2 can be set by jumper
6> all I/O lead out with marked names for further application
7> supports USB power input(5V) and JLink Power input.
8> Board size 71 (mm) * 93 (mm)
2> Onboard Standard JTAG interface and reset button
3> 2 Onboard crystals, 32.768KHZ and 8MHZ
4> Onboard DC Regulator AMS1117-3.3: 5V input to 3.3V
5> One RS232 serial port, UART1 and UART2 can be set by jumper
6> all I/O lead out with marked names for further application
7> supports USB power input(5V) and JLink Power input.
8> Board size 71 (mm) * 93 (mm)
Xilinx Spartan-3E XC3S250-VQ100 FPGA development board
I have the digilent XC3100 Basys board but this was a welcomed upgrade since I want more resource to be able to experiment with processor cores in the future. A nice $40 (total including shipping) purchase from Ebay
See pictures
See pictures
Tuesday, July 16, 2013
Adventures In MICROCONTROLLER and FPGA development
so this is going to replace my current blog on livejournal.com. this seems to be a better interface for blogging and especially posting my code and examples and tracking progress.
current projects in the works for the next few months revolve around
ARM cortex-M3
USB
FPGA (Xilinx)
At the same time. My next post will detail the hardware I have acquired and some code I have begun to put together. Its funny .. because prior to this I was doing USB firmware development on the NXP/Phillips ARM7TDMI lpc2378 until it died.
This oddly enough gave me the opportunity to look into other NON NXP boards and I decided now (as any) would be a good time to plunge into cortex-M3 and I am glad I did ... its designed very well and simpler to develop under
More later
current projects in the works for the next few months revolve around
ARM cortex-M3
USB
FPGA (Xilinx)
At the same time. My next post will detail the hardware I have acquired and some code I have begun to put together. Its funny .. because prior to this I was doing USB firmware development on the NXP/Phillips ARM7TDMI lpc2378 until it died.
This oddly enough gave me the opportunity to look into other NON NXP boards and I decided now (as any) would be a good time to plunge into cortex-M3 and I am glad I did ... its designed very well and simpler to develop under
More later
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