Phase 1: Script files

$HOME/.gdbinit

set history filename ~/.gdb_history
set history save
set architecture arm
target remote localhost:3333
monitor reset halt 

$HOME/.bashrc

alias openocd_ft2232='sudo /usr/local/bin/openocd -s /home/rombios/DEVEL/EGWU/openocd/scripts -f interface/egwu_interface_usb.cfg -f board/egwu_board.cfg'
alias openocd_ftdi='sudo /usr/bin/openocd -s /home/rombios/DEVEL/EGWU/openocd/scripts -f interface/ftdi/egwu_interface_usb.cfg -f board/egwu_board.cfg' 

$HOME/DEVEL/EGWU/openocd/scripts/board

# egwu_board.cfg

set WORKAREASIZE 0x10000
source [find target/egwu_target_1788.cfg] 

$HOME/DEVEL/EGWU/openocd/scripts/interface

#
# embedded projects openocd usb adapter v3
#
# http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=14
#

#gdb_port        10000
interface  ft2232
ft2232_vid_pid  0x0403 0x6010
ft2232_device_desc "Dual RS232-HS"
ft2232_layout  "usbjtag"
ft2232_latency  2  

$HOME/DEVEL/EGWU/openocd/scripts/interface/ftdi

#
# embedded projects openocd usb adapter v3
#
# http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=14
#

interface   ftdi
ftdi_vid_pid   0x0403 0x6010
#ftdi_channel     0
ftdi_layout_init 0x1000 0x3d1b 

$HOME/DEVEL/EGWU/openocd/scripts/target

# egwu_target_1788.cfg

set CHIPNAME  lpc1788
set CPUTAPID  0x4ba00477
set CPURAMSIZE  0x10000
set CPUROMSIZE  0x80000

# CCLK is the core clock frequency in KHz

set CCLK 8000
source [find target/egwu_target_17xx.cfg];
cortex_m reset_config sysresetreq

# egwu_target_17xx.cfg

if { [info exists CHIPNAME] } {
 set _CHIPNAME $CHIPNAME
} else {
 error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
if { [info exists CCLK] } {
 set _CCLK $CCLK
} else {
 set _CCLK 12000
}

if { [info exists CPUTAPID] } {
 set _CPUTAPID $CPUTAPID
} else {
 error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

if { [info exists CPURAMSIZE] } {
  set _CPURAMSIZE $CPURAMSIZE
} else {
 error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

if { [info exists CPUROMSIZE] } {
  set _CPUROMSIZE $CPUROMSIZE
} else {
 error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME

# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE

# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code
# (including a boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
 lpc1700 $_CCLK calc_checksum

# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
adapter_khz 2000
#adapter_khz 1000

# delays on reset lines
adapter_nsrst_assert_width 50
adapter_nsrst_delay  100

jtag_ntrst_assert_width  50
jtag_ntrst_delay   100

$_TARGETNAME configure -event reset-init {
 mww 0x400FC040 0x01
 mww 0xe000ed08 0x10000000
}

# perform a soft reset
#cortex_m reset_config sysresetreq
cortex_m reset_config trst_only

$HOME/DEVEL/EGWU/linker/IE_lpc17xx.ld

/*
 ***********************************************************************
 *name:         IE_lpc177x.ld
 *author:       Samuel Igwe
 *date:         06/10/2015
 *description:  linker script that I have created for use in egwu
 *              development related matters on this board
 *
 *  first this is the memory map I had decided on 
 *    
 *         0xa1ff ffff  +++++++++++++++++++++++++++++++
 *                  +ext sdram  = 64Mb            +
 *              0xa000 0000   +++++++++++++++++++++++++++++++
 *                 +                             +
 *         0x8001 ffff  +++++++++++++++++++++++++++++++
 *                  +ext sram   = 128k            +
 *              0x8000 0000   +++++++++++++++++++++++++++++++
 *                 +                             +
 *         0x1000 ffff  +++++++++++++++++++++++++++++++
 *                  +int sram   = 64k             +
 *              0x1000 0000   +++++++++++++++++++++++++++++++
 *                 +                             +
 *  0x0007 ffff  +++++++++++++++++++++++++++++++
 *                 +int flash  = 512k            +
 *  0x0000 0000  +++++++++++++++++++++++++++++++
 *
 *
 *              for now I will be debugging from SRAM until the code 
 *  matures
 *
 *  adding the variable _loadaddr_data_section_ to the end
 *  of the .text along with the AT> directive places a copy
 *  of the .data right after .text but leaves the virtual
 *  addresses pointing at .data in ram
 *  
 *  in the assembler initialization file I can copy .data 
 *  from bottom of .text into .data in sram
 ***********************************************************************
 */
MEMORY  {
        LPC177X_RAM    : ORIGIN = 0x10000000,   LENGTH = (64K - 1024)
        }



SECTIONS
        {
        .data :   
                {
                *(.data);
                } > LPC177X_RAM

        .text :   
  {
                *(.text);
                *(.rodata);
                } > LPC177X_RAM

        .bss :
                {
                *(.bss);
                } > LPC177X_RAM
        }