per lpc1778 manual:
with the appropriate bias caps CX1 and CX2, setting bits 4 (oscillator range select) and 5 (main oscillator enable) of the System Control and Status register should return read only bit 6 (oscillator status) as ready.
This wasnt happening and I thought perhaps it was because I chose 12pf for bias caps from an earlier crystal selection before I bought the 24Mhz versions on ebay.
The datasheet says using capacitor values 18pf or 39pf depending on crystal load capacitance. I ordered 18pf and 39pf 0603's on ebay. And replaced the 12pf on the board ... TO NO AVAIL
With phase 2 nearing completion (and me needing a precise crystal clock source for the SDRAM controller/USB interface and FPGA) I decided to revisit the schematic and noticed that I had shorted XTAL1 pin to ground via 0ohm resistor R13. Why I put that in the design I dont know ... and I have to go to storage to find the notebooks I made notes on when I designed this board.
What I do know is that it doesnt belong there. So I brought out my hot air tool and removed R13
Then I launched GDB to see if the oscillator status changes after I enable the logic driver and sure enough it does.
(gdb) monitor reset halt
JTAG tap: lpc1788.cpu tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4)
Only resetting the Cortex-M core, use a reset-init event handler to reset any peripherals or configure hardware srst support.
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x1fff0080 msp: 0x10001ffc
(gdb) monitor mdw 0x400fc1a0
0x400fc1a0: 00000009
(gdb) monitor mww 0x400fc1a0 0x39
(gdb) monitor mdw 0x400fc1a0
0x400fc1a0: 00000079
I removed R13 on the other spare EGWU board with CX1/CX2 bias caps of 12pf and tested it and it worked as well.
The next few days will be devoted to debugging UARTIO code and writing the YModem transfer code ... before delving in the SDRAM controller
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