EGWU arm-linux-gnueabi-gdb $HOME/.gdbinit

$HOME/.gdbinit
set history filename ~/.gdb_history
set history save
target remote localhost:3333
monitor reset halt



Decided to dump the CPUID register which should read back
0x412fc230 



arm-linux-gnueabi-gdb
GNU gdb (GDB) 7.0.1-debian
Copyright (C) 2009 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=i486-linux-gnu --target=arm-linux-gnueabi".
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
0x00000000 in ?? ()
JTAG tap: lpc1788.cpu tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4)

target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x1fff0080 msp: 0x10001ffc
(gdb)
(gdb) monitor reset halt
JTAG tap: lpc1788.cpu tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4)
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x1fff0080 msp: 0x10001ffc
(gdb) monitor mdw 0xe000ed00
0xe000ed00: 412fc230
(gdb)

EGWU openocd 0.7.0 connection established

Finally!!!
So
sudo openocd -f interface/egwu_interface.cfg -f board/egwu_board.cfg


Open On-Chip Debugger 0.7.0 (2015-03-16-10:11)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
adapter_nsrst_delay: 200
jtag_ntrst_delay: 200
adapter speed: 10 kHz
cortex_m3 reset_config vectreset
cortex_m3 reset_config sysresetreq
Info : max TCK change to: 30000 kHz
Info : clock speed 10 kHz
Info : JTAG tap: lpc1788.cpu tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4)
Info : lpc1788.cpu: hardware has 6 breakpoints, 4 watchpoints

EGWU openocd 0.7.0 egwu_interface_usb.cfg

I grabbed the first fully assembled board from storage to test this morning and got the same results. very disheartening. I thought then I should focus on the ft2232_layout. I couldnt find "oocdlink" pin layouts in the first few google searches. But I found the one for "usbjtag" in the openocd thesis on www.openocd.org/files/thesis.pdf on page 6.

This of course matched the FTDI application note AN_129 (Interfacing FTDI USB Hi-Speed Devices to a JTAG TAP) which I based my design on.










cd /usr/local/share/openocd/scripts/interface
cp openocd-usb-hs.cfg egwu_interface_usb.cfg
change oocdlink to usbjtag below



#
# embedded projects openocd usb adapter v3
#
# http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=14
#

interface ft2232
ft2232_vid_pid 0x0403 0x6010
ft2232_device_desc "Dual RS232-HS"
ft2232_layout "usbjtag"
ft2232_latency 2

EGWU openocd.0.7.0 olimex jtag tiny

Rigged up the olimex JTAG tiny to plug into the 7 pin ARM-JTAG P8 connector. Same results. So this tells me there is a problem possibly with the lpc1778 chip or the JTAG pins. Once I buzz them out later tonight Ill have to seriously check for short and opens or consider that this chip may have been damaged during board assembly and to prepare to replace it ;(



sudo openocd -f interface/olimex-jtag-tiny.cfg -f board/egwu_board.cfg


[sudo] password for rombios:
Open On-Chip Debugger 0.7.0 (2015-03-16-10:11)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
adapter_nsrst_delay: 200
jtag_ntrst_delay: 200
adapter speed: 10 kHz
cortex_m3 reset_config vectreset
cortex_m3 reset_config sysresetreq
Info : clock speed 10 kHz
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: lpc1788.cpu: IR capture error; saw 0x0f not 0x01
Warn : Bypassing JTAG setup events due to errors
Warn : Invalid ACK 0x7 in JTAG-DP transaction
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 100ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 300ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 700ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 1500ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 3100ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 6300ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 6300ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 6300ms

EGWU openocd 0.7.0 initialization

the order of script files passed to openOCD matters. the order should be
interface, board, target


sudo openocd -f interface/openocd-usb-hs.cfg -f board/egwu_board.cfg





Open On-Chip Debugger 0.7.0 (2015-03-16-10:11)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
adapter_nsrst_delay: 200
jtag_ntrst_delay: 200
adapter speed: 10 kHz
cortex_m3 reset_config vectreset
cortex_m3 reset_config sysresetreq
Info : max TCK change to: 30000 kHz
Info : clock speed 10 kHz
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: lpc1788.cpu: IR capture error; saw 0x0f not 0x01
Warn : Bypassing JTAG setup events due to errors
Warn : Invalid ACK 0x7 in JTAG-DP transaction
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 100ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 300ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 700ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 1500ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 3100ms
Polling target lpc1788.cpu failed, GDB will be halted. Polling again in 6300ms

EGWU openocd 0.7.0 openocd-usb-hs.cfg

openocd-usb-hs.cfg is used as is unmodified
cd /usr/local/share/openocd/scripts/interface


#
# embedded projects openocd usb adapter v3
#
# http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=14
#

interface ft2232
ft2232_vid_pid 0x0403 0x6010
ft2232_device_desc "Dual RS232-HS"
ft2232_layout "oocdlink"
ft2232_latency 2

EGWU openocd 0.7.0 egwu_target_17xx.cfg

use lpc17xx as baseline for egwu_target_17xx. modifications as necessary
cd /usr/local/share/openocd/scripts/target
cp lpc17xx.cfg egwu_target_17xx.cfg



# Main file for NXP LPC17xx Cortex-M3
#
# !!!!!!
#
# This file should not be included directly, rather
# by the lpc1751.cfg, lpc1752.cfg, etc. which set the
# needed variables to the appropriate values.
#
# !!!!!!

# LPC17xx chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
# source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
} else {
    error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
if { [info exists CCLK] } {
    set _CCLK $CCLK
} else {
    set _CCLK 4000
}

if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
} else {
    error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

if { [info exists CPURAMSIZE] } {
  set _CPURAMSIZE $CPURAMSIZE
} else {
    error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

if { [info exists CPUROMSIZE] } {
  set _CPUROMSIZE $CPUROMSIZE
} else {
    error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
}

#delays on reset lines
adapter_nsrst_delay 200
jtag_ntrst_delay 200

jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
#swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME

# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE

# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code
# (including a boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
    lpc1700 $_CCLK calc_checksum

# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
adapter_khz 10

$_TARGETNAME configure -event reset-init {
    # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
    # "User Flash Mode" where interrupt vectors are _not_ remapped,
    # and reside in flash instead).
    #
    # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
    # Bit Symbol Value Description Reset
    # value
    # 0 MAP Memory map control. 0
    # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
    # 1 User mode. The on-chip Flash memory is mapped to address 0.
    # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
    #
    # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user

    mww 0x400FC040 0x01
}

# if srst is not fitted use VECTRESET to
# perform a soft reset - SYSRESETREQ is not supported
cortex_m reset_config vectreset

EGWU openocd 0.7.0 egwu_target_1788.cfg

use lpc1788 as base line for egwu_target_1788. make necessary modifications

cd /usr/local/share/openocd/scripts/target
cp lpc1788.cfg egwu_target_lpc1788.cfg



# NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB Local On-Chip SRAM,
set CHIPNAME lpc1788
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x10000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~12MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 12000

#Include the main configuration file.
source [find target/egwu_target_17xx.cfg];

# if srst is not fitted, use SYSRESETREQ to perform a soft reset
cortex_m reset_config sysresetreq

EGWU openocd 0.7.0 egwu_board.cfg

use stm's cortex-m3 board script as baseline for egwu' board script

cd /usr/local/share/openocd/scripts/board
cp olimex_stm32_h107.cfg egwu_board.cfg



# Work-area size (RAM size) = 64kB
set WORKAREASIZE 0x10000
#transport select jtag

source [find target/egwu_target_1788.cfg]

EGWU on the road to USB JTAG debugging

The reason I wasnt seeing a clock on CLKOUT pin (NXP cortex-m3) was because on default OSC_EN and CLK_OUT are turned off. Why would this make any sense? Well NXP's ARM chips include an onboard RC oscillator.

Its 8Mhz for the cortex-M3 variants. So technically you could run a small embedded system without an external oscillator or crystal.

You wont be able to deal with precise timing but for a system that doesnt require it, this would suffice.

But even before that I have got to get JTAG communication working. I could go the pin header route (the 7 pins of P8) are tied to the 5 JTAG pins on the lpc1778 and to 3.3v and gnd. I have got the Olimex JTAG dongle and I can rig up male to female pin header cables to attach to the P8 connector on the board.

But I dont want to do that. That would defeat the purpose of putting an FTD2232H on the board. Not a cheap IC by any means.

OpenOCD supports USBJTAG. I knew this going in but I didnt check its GPIO mapping to see if its identical to mine. In either case its programmable so Ill end up probably having to recompile openocd 0.8.0 later anyway.

For now my primary goal was just to verify that once I plugged in a cable between my Linux development laptop and EGWU's J4 mini-USB connector, it enumerates correctly. Easy to verify with "lsusb"

AND it does


rombios@igboembedded:~$ lsusb
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
Bus 003 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub

rombios@igboembedded:~$ lsusb
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
Bus 003 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
Bus 001 Device 002: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC

rombios@igboembedded:~$ dmesg |tail
[  148.324678] usb 1-1: FTDI USB Serial Device converter now attached to ttyUSB0
[  148.324702] ftdi_sio 1-1:1.1: FTDI USB Serial Device converter detected
[  148.325218] usb 1-1: Detected FT2232H
[  148.325222] usb 1-1: Number of endpoints 2
[  148.325225] usb 1-1: Endpoint 1 MaxPacketSize 512
[  148.325228] usb 1-1: Endpoint 2 MaxPacketSize 512
[  148.325231] usb 1-1: Setting MaxPacketSize 512
[  148.327030] usb 1-1: FTDI USB Serial Device converter now attached to ttyUSB1
[  148.327343] usbcore: registered new interface driver ftdi_sio
[  148.327347] ftdi_sio: v1.6.0:USB FTDI Serial Converters Driver

EGWU its alive ...

Busy weekend - catching up on sleep. Finally got around to powering up the first prototype. First I had to put away the hotplate and reflow tools, clear away some space and set aside stuff thats destined for storage and mount the scope in a safe area where my 18 month old isnt tempted to get at it.

Initial power up looks good. The three regulator outputs are as expected. Felt around the various Ic's and none felt warm - so looks like there isnt a short I have to deal with, for now

But I didnt get any signal out of the crystal/oscillator inputs to the Cortex-M3. Ill have to investigate this later ... its 5am and I am turning in.