IE_stm32_timer.h

/*
 **********************************************************************
 *name:         IE_stm32_timer.h
 *author:       Samuel Igwe
 *date:         08/27/2013
 *description:  Igbo Embedded stm32_timer header
 **********************************************************************
 */
#ifndef IE_STM32_TIMER
#define IE_STM32_TIMER


#define PTR_STM32_TIM2_BASE                             0x40000000 
#define PTR_STM32_TIM3_BASE                             0x40000400 
#define PTR_STM32_TIM4_BASE                             0x40000800 
#define PTR_STM32_TIM5_BASE                             0x40000c00 



/*
 **********************************************************************
 *timer #defines
 *basic timers 6 and 7 arent supported on the stm32f103. but general
 *purpose timers 2 through 5 are supported
 *
 *these timers are driven off a 36Mhz clock (sysclk / 2) which is the
 *maximum on the APB1 bus
 **********************************************************************
 **********************************************************************
 *control register 1
 **********************************************************************
 */
#define PTR_STM32_TIM2_CR1      (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x0)
#define PTR_STM32_TIM3_CR1      (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x0)
#define PTR_STM32_TIM4_CR1      (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x0)
#define PTR_STM32_TIM5_CR1      (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x0)
        #define STM32_TIM_CR1_CKD_MASK                  (0x3 << 8)
        #define STM32_TIM_CR1_CKD_TCK                   (0 << 8)
        #define STM32_TIM_CR1_CKD_2TCK                  (1 << 8)
        #define STM32_TIM_CR1_CKD_4TCK                  (2 << 8)

        #define STM32_TIM_CR1_ARPE                      (1 << 7)

        #define STM32_TIM_CR1_CMS_MASK                  (0x3 << 5)
        #define STM32_TIM_CR1_CMS_EDGE                  (0 << 5)
        #define STM32_TIM_CR1_CMS_MODE1                 (1 << 5)
        #define STM32_TIM_CR1_CMS_MODE2                 (2 << 5)
        #define STM32_TIM_CR1_CMS_MODE3                 (3 << 5)

        #define STM32_TIM_CR1_DIR_MASK                  (1 << 4)
        #define STM32_TIM_CR1_DIR_UP                    (0 << 4)
        #define STM32_TIM_CR1_DIR_DOWN                  (1 << 4)

        #define STM32_TIM_CR1_OPM                       (1 << 3)
        #define STM32_TIM_CR1_URS                       (1 << 2)
        #define STM32_TIM_CR1_UDIS                      (1 << 1)
        #define STM32_TIM_CR1_CEN                       (1 << 0)



/*
 **********************************************************************
 *control register 2
 **********************************************************************
 */
#define PTR_STM32_TIM2_CR2      (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x4)
#define PTR_STM32_TIM3_CR2      (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x4)
#define PTR_STM32_TIM4_CR2      (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x4)
#define PTR_STM32_TIM5_CR2      (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x4)
        #define STM32_TIM_CR2_MMS_TI1S                  (0x1 << 7)

        #define STM32_TIM_CR2_MMS_MASK                  (0x7 << 4)
        #define STM32_TIM_CR2_MMS_RESET                 (0x0 << 4)
        #define STM32_TIM_CR2_MMS_ENABLE                (0x1 << 4)
        #define STM32_TIM_CR2_MMS_UPDATE                (0x2 << 4)
        #define STM32_TIM_CR2_MMS_PULSE                 (0x3 << 4)

        #define STM32_TIM_CR2_CCDS                      (0x1 << 3)



/*
 **********************************************************************
 *dma interrupt enable register
 **********************************************************************
 */
#define PTR_STM32_TIM2_DIER     (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0xc)
#define PTR_STM32_TIM3_DIER     (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0xc)
#define PTR_STM32_TIM4_DIER     (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0xc)
#define PTR_STM32_TIM5_DIER     (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0xc)
        #define STM32_TIM_DIER_UDE                      (1 << 8)
        #define STM32_TIM_DIER_CC4IE                    (1 << 4)
        #define STM32_TIM_DIER_CC3IE                    (1 << 3)
        #define STM32_TIM_DIER_CC2IE                    (1 << 2)
        #define STM32_TIM_DIER_CC1IE                    (1 << 1)
        #define STM32_TIM_DIER_UIE                      (1 << 0)



/*
 **********************************************************************
 *status register
 **********************************************************************
 */
#define PTR_STM32_TIM2_SR       (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x10)
#define PTR_STM32_TIM3_SR       (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x10)
#define PTR_STM32_TIM4_SR       (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x10)
#define PTR_STM32_TIM5_SR       (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x10)
        #define STM32_TIM_SR_CC4IF                      (1 << 4)
        #define STM32_TIM_SR_CC3IF                      (1 << 3)
        #define STM32_TIM_SR_CC2IF                      (1 << 2)
        #define STM32_TIM_SR_CC1IF                      (1 << 1)
        #define STM32_TIM_SR_UIF                        (1 << 0)



/*
 **********************************************************************
 *event generation register
 **********************************************************************
 */
#define PTR_STM32_TIM2_EGR      (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x14)
#define PTR_STM32_TIM3_EGR      (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x14)
#define PTR_STM32_TIM4_EGR      (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x14)
#define PTR_STM32_TIM5_EGR      (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x14)
        #define STM32_TIM_EGR_CC4G                      (1 << 4)
        #define STM32_TIM_EGR_CC3G                      (1 << 3)
        #define STM32_TIM_EGR_CC2G                      (1 << 2)
        #define STM32_TIM_EGR_CC1G                      (1 << 1)
        #define STM32_TIM_EGR_UG                        (1 << 0)



/*
 **********************************************************************
 *capture/compare enable register
 **********************************************************************
 */
#define PTR_STM32_TIM2_CCER     (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x20)
#define PTR_STM32_TIM3_CCER     (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x20)
#define PTR_STM32_TIM4_CCER     (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x20)
#define PTR_STM32_TIM5_CCER     (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x20)
        #define STM32_TIM_CCER_CC4E                     (1 << 12)
        #define STM32_TIM_CCER_CC3E                     (1 << 8)
        #define STM32_TIM_CCER_CC2E                     (1 << 4)
        #define STM32_TIM_CCER_CC1E                     (1 << 0)



/*
 **********************************************************************
 *counter register
 **********************************************************************
 */
#define PTR_STM32_TIM2_CNT      (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x24)
#define PTR_STM32_TIM3_CNT      (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x24)
#define PTR_STM32_TIM4_CNT      (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x24)
#define PTR_STM32_TIM5_CNT      (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x24)



/*
 **********************************************************************
 *prescaler register
 **********************************************************************
 */
#define PTR_STM32_TIM2_PSC      (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x28)
#define PTR_STM32_TIM3_PSC      (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x28)
#define PTR_STM32_TIM4_PSC      (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x28)
#define PTR_STM32_TIM5_PSC      (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x28)



/*
 **********************************************************************
 *auto reload register
 **********************************************************************
 */
#define PTR_STM32_TIM2_ARR      (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x2c)
#define PTR_STM32_TIM3_ARR      (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x2c)
#define PTR_STM32_TIM4_ARR      (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x2c)
#define PTR_STM32_TIM5_ARR      (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x2c)



/*
 **********************************************************************
 *capture/compare register 1
 **********************************************************************
 */
#define PTR_STM32_TIM2_CCR1     (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x34)
#define PTR_STM32_TIM3_CCR1     (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x34)
#define PTR_STM32_TIM4_CCR1     (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x34)
#define PTR_STM32_TIM5_CCR1     (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x34)



/*
 **********************************************************************
 *capture/compare register 2
 **********************************************************************
 */
#define PTR_STM32_TIM2_CCR2     (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x38)
#define PTR_STM32_TIM3_CCR2     (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x38)
#define PTR_STM32_TIM4_CCR2     (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x38)
#define PTR_STM32_TIM5_CCR2     (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x38)



/*
 **********************************************************************
 *capture/compare register 3
 **********************************************************************
 */
#define PTR_STM32_TIM2_CCR3     (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x3c)
#define PTR_STM32_TIM3_CCR3     (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x3c)
#define PTR_STM32_TIM4_CCR3     (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x3c)
#define PTR_STM32_TIM5_CCR3     (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x3c)



/*
 **********************************************************************
 *capture/compare register 4
 **********************************************************************
 */
#define PTR_STM32_TIM2_CCR4     (volatile unsigned int *)(PTR_STM32_TIM2_BASE + 0x40)
#define PTR_STM32_TIM3_CCR4     (volatile unsigned int *)(PTR_STM32_TIM3_BASE + 0x40)
#define PTR_STM32_TIM4_CCR4     (volatile unsigned int *)(PTR_STM32_TIM4_BASE + 0x40)
#define PTR_STM32_TIM5_CCR4     (volatile unsigned int *)(PTR_STM32_TIM5_BASE + 0x40)



#endif